1
Masato Motomura: Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same. NEC Corporation, Hayes Soloway Hennessey Grossman & Hage P C, January 9, 2001: US06172521 (165 worldwide citation)

In order to achieve rapid reconfiguration of logic elements in a programmable logic device, a plurality of memory logic modules are arranged in a two-dimensional array. At least one logic element is provided in each of the plurality of memory logic modules. The logic element is provided with a confi ...


2
Masato Motomura: Line buffer type semiconductor memory device capable of direct prefetch and restore operations. NEC Corporation, February 12, 2002: US06347055 (148 worldwide citation)

In a line buffer type semiconductor memory device contructed by a memory section and a line buffer section including a plurality of line buffers each capable of storing data of one segment size, a direct fetch control section reads first data of one segment size from the memory section and writes th ...


3
Masato Motomura: Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof. NEC Corporation, McGinn & Gibb PLLC, January 8, 2002: US06338108 (86 worldwide citation)

A memory section and coprocessor sections in a coprocessor-integrated packet-type DRAM are provided with unique memory device ID and coprocessor device IDs respectively. The coprocessor-integrated packet-type DRAMs are connected to a single bus master type packet-type memory/coprocessor bus via exte ...


4
Masato Motomura: Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads. NEC Corporation, Foley & Lardner, April 21, 1998: US05742822 (80 worldwide citation)

A multithreaded processor includes an instruction pipelined unit 140 and a register file 120 composed of a plurality of register banks 130. The register file 120 is coupled to an external memory 190 through register frame load/store lines 121, so that a register frame, which is defined as a content ...


5
Masato Motomura, Yoshikazu Yabe, Yoshiharu Aimoto: Memory integrated circuit and main memory and graphics memory systems applying the above. NEC Corporation, Sughrue Mion Zinn Macpeak & Seas PLLC, July 17, 2001: US06263413 (59 worldwide citation)

A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed ...


6
Koichiro Furuta, Taro Fujii, Masato Motomura: Programmable device with an array of programmable cells and interconnection network. NEC Corporation, Young & Thompson, August 28, 2001: US06281703 (55 worldwide citation)

The present invention provide a programmable device comprising: an array of plural programmable cells; a first sub-interconnection network comprising a plurality of first interconnections which extend to surround each of the plural programmable cells for transmitting data; and a second sub-interconn ...


7
Masato Motomura: Parallel processor for executing plural thread program in parallel using virtual thread numbers. NEC Corporation, Foley & Lardner, September 29, 1998: US05815727 (41 worldwide citation)

A parallel processor system executing a program consisted of a plurality of threads in parallel per threads, includes thread generating portion for managing three states of executing state, executable state and waiting state as states of the threads and generating other thread in the executable stat ...


8
Taro Fujii, Masato Motomura, Koichiro Furuta: Array type processor with state transition controller identifying switch configuration and processing element instruction address. NEC Corporation, Dickstein Shapiro Morin & Oshinsky, May 18, 2004: US06738891 (31 worldwide citation)

To execute all processing in an array section of an array-type processor, each processor must execute processing of different types, i.e., processing of an operating unit and processing of a random logic circuit, which limits its size and processing performance. A data path section including process ...


9
Masato Motomura: Microprocessor having register file. NEC Corporation, Foley & Lardner, January 27, 1998: US05713038 (25 worldwide citation)

A microprocessor 1 is coupled to a memory 2, and includes an instruction pipeline 3 and a register file 4. The register file 4 includes an address read/write circuit 5, a plurality of frame address storing registers 6 coupled to the address read/write circuit 5, data read/write circuits 7 and 10, an ...


10
Masato Motomura, Tadayoshi Enomoto: Motion picture coder and system for controlling the same. NEC Corporation, Young & Thompson, February 28, 1995: US05394189 (14 worldwide citation)

A motion picture coder for coding plural macro blocks of motion picture data based on a standardizing system is disclosed. The coder comprises first and second pipe-lined processors executing different coding processes respectively, both of which are separated from one another so as to accomplish a ...