1
Masataka Takano, Yoji Oka, Akihiko Takase, Setsuo Takahashi: Path changing system and method for use in ATM communication apparatus. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, February 4, 1997: US05600630 (132 worldwide citation)

An ATM path changing system and method for use in an ATM communication apparatus and ATM communication network are provided which can set an alternating route in the event of a failure occurring in a transmission line or VP. A header converter in a line controller includes a plurality of output path ...


2
Masataka Takano, Yoji Oka, Akihiko Takase, Setsuo Takahashi: Path changing system and method for use in ATM communication apparatus. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, July 20, 1999: US05926456 (51 worldwide citation)

An ATM path changing system and method for use in an ATM communication apparatus and ATM communication network are provided which can set an alternating route in the event of a failure occurring in a transmission line or VP. A header converter in a line controller includes a plurality of output path ...


3
Noboru Endo, Masataka Takano: Aim switching system and path changing method. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, June 9, 1998: US05764624 (34 worldwide citation)

An ATM switching system at each node of a network performs route changing or rerouting promptly when a failure occurs. In each of ATM switching systems at nodes N1 to N6: a route table 21 of a line interface 102 is set with conversion header information of a normal route, and an alternate routing ta ...


4
Kaoru Aoki, Masataka Takano, Junichirou Yanagi, Tetsushi Nakano, Miho Iino: ATM communication system. Hitachi, Antonelli Terry Stout & Kruas, April 14, 1998: US05740158 (21 worldwide citation)

An ATM communication system including a plurality of communication nodes connected in a loop form by buses, buffers disposed in each communication node, a synchronizing pulse generation circuit for conducting cell demultiplexing of all communication nodes at the same timing, storage devices disposed ...


5
Kaoru Aoki, Masataka Takano, Junichirou Yanagi, Tetsushi Nakano, Miho Iino: ATM communication system having a physical loop form with logical start point and end point. Hitachi, Antonelli Terry Stout & Kraus, February 18, 1997: US05604729 (12 worldwide citation)

An ATM communication system including a plurality of communication nodes connected in a loop form by buses, buffers disposed in each communication node, a synchronizing pulse generation circuit for conducting cell demultiplexing of all communication nodes at the same timing, storage devices disposed ...


6
Masataka Takano, Toshihide Fujio: Bus type clock supplying system for providing a clock in a communication system with a plurality of clock bus lines. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, May 20, 1997: US05631931 (11 worldwide citation)

A bus type clock supplying system in a communication system with master-slave synchronization includes communication cards connected with transmission lines within a communication system and a clock bus. Each communication card includes a clock supplying section including a frequency divider for ext ...


7
Yasushi Fukuda, Masataka Takano, Setsuo Takahashi: Switching system and subscribers circuit controlling apparatus. Hitachi, Antonelli Terry Stout & Kraus, April 4, 1995: US05404389 (7 worldwide citation)

A switching system which includes subscriber's circuit device connected to terminals and a subscriber's circuit controlling apparatus between a host apparatus and subscriber's circuit devices for controlling the subscriber's circuit devices in accordance with a control order corresponding to control ...


8
Kaoru Aoki, Masataka Takano, Junichiro Yanagi: Atm communication system. Hitachi, DONG WEI YE KAIDONG, November 22, 1995: CN94113760

An ATM communication system including a plurality of communication nodes connected in a loop form by buses, buffers disposed in each communication node, a synchronizing pulse generation circuit for conducting cell demultiplexing of all communication nodes at the same timing, storage devices disposed ...