1
Takashi Kato, Masao Taguchi: Three-dimensional integrated circuit and manufacturing method thereof. Fujitsu, Staas & Halsey, July 3, 1990: US04939568 (334 worldwide citation)

The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. I ...


2
Masao Taguchi, Taiji Ema: Method of producing a dynamic random access memory device. Fujitsu, Armstrong Nikaido Marmelstein Kubovcik & Murray, December 10, 1991: US05071783 (63 worldwide citation)

A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film w ...


3
Masao Taguchi, Yasurou Matsuzaki: Dynamic memory circuit with automatic refresh function. Fujitsu, Arent Fox Kintner Plotkin & Kahn PLLC, August 20, 2002: US06438055 (54 worldwide citation)

The present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs ...


4
Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga: Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation. Fujitsu, Nikaido Marmelstein Murray & Oram, September 17, 1996: US05557221 (50 worldwide citation)

A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this ...


5
Masao Taguchi: Semiconductor memory device having a testing function and method of testing the same. Fujitsu, Armstrong Westerman Hattori McLeland & Naughton, August 16, 1994: US05339273 (47 worldwide citation)

A semiconductor memory device is provided with a plurality of bit lines, a plurality of word lines, a memory cell array including a plurality of memory cells each coupled to one bit line and one word line, and a varying part for varying a capacitance of at least a selected one of the bit lines in re ...


6
Yasurou Matsuzaki, Hiroyoshi Tomita, Masao Taguchi: Semiconductor memory device for operating in synchronization with edge of clock signal. Fujitsu, Arent Fox Kintner Plotkin & Kahn, January 21, 2003: US06510095 (40 worldwide citation)

A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response ...


7
Yoshihiro Takemae, Masao Taguchi, Masao Nakano, Takaaki Suzuki, Hiroyoshi Tomita, Toshiya Uchida, Yasuharu Sato, Atsushi Hatakeyama, Masato Matsumiya, Yasurou Matsuzaki: Semiconductor device and semiconductor system for high-speed data transfer. Fujitsu, Nikaido Marmelstein Murray & Oram, June 20, 2000: US06078514 (39 worldwide citation)

A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip ...


8
Masao Taguchi, Yasurou Matsuzaki, Miki Yanagawa: Semiconductor device using complementary clock and signal input state detection circuit used for the same. Fujitsu, Arent Fox Kintner Plotkin & Kahn PLLC, August 15, 2000: US06104225 (38 worldwide citation)

A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input cir ...


9
Masao Taguchi, Taiji Ema: Dynamic random access memory device and method of producing same. Fujitsu, Armstrong Nikaido Marmelstein Kubovcik & Murray, November 27, 1990: US04974040 (37 worldwide citation)

A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film w ...


10
Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima: Variable delay circuit and semiconductor integrated circuit device. Fujitsu, Arent Fox Kintner Plotkin & Kahn PLLC, April 11, 2000: US06049239 (36 worldwide citation)

A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.