1
Masaki Momodomi, Fujio Masuoka, Riichiro Shirota, Yasuo Itoh, Kazunori Ohuchi, Ryouhei Kirisawa: Electrically erasable programmable read-only memory with NAND cell structure. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, September 25, 1990: US04959812 (393 worldwide citation)

An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a contro ...


2
Masaki Momodomi, Riichiro Shirota, Yasuo Itoh, Satoshi Inoue, Fujio Masuoka, Ryozo Nakayama, Ryouhei Kirisawa: Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, July 3, 1990: US04939690 (99 worldwide citation)

An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. W ...


3
Koji Sakui, Hiroshi Nakamura, Tomoharu Tanaka, Masaki Momodomi, Fujio Masuoka, Kazunori Ohuchi, Tetsuo Endoh: Semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, June 4, 1996: US05523980 (75 worldwide citation)

A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data theref ...


4
Mitsugi Ogura, Masaki Momodomi: MOS dynamic ram. Kabushiki Kaisha Toshiba, Oblon Fisher Spivak McClelland & Maier, December 16, 1986: US04630088 (74 worldwide citation)

A MOS dynamic RAM consists of integrated memory cells each having a MOSFET and a MOS capacitor. The MOS dynamic RAM comprises a semiconductor substrate of a first conductivity type on which periodic projections and recesses are formed, a source region of a second conductivity type formed in the uppe ...


5
Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige: Non-volatile semiconductor memory device and memory system using the same. Kabushiki Kaisha Toshiba, Foley & Lardner, November 1, 1994: US05361227 (70 worldwide citation)

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly execu ...


6
Yoshiyuki Tanaka, Yasuo Itoh, Masaki Momodomi, Yoshihisa Iwata, Tomoharu Tanaka: NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, January 11, 1994: US05278794 (62 worldwide citation)

A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and ...


7
Hiroshi Nakamura, Masaki Momodomi, Yoshihisa Iwata, Ryouhei Kirisawa: Semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, June 16, 1998: US05768195 (58 worldwide citation)

A semiconductor memory device according to he present invention comprises a first conductivity-type semiconductor substrate in which a second conductivity-type well is formed, a memory cell array composed of a plurality of memory cells arranged in a matrix in the second conductivity-type well, and a ...


8
Seiichi Aritome, Riichiro Shirota, Ryouhei Kirisawa, Yoshihisa Iwata, Masaki Momodomi: Electrically erasable programmable read-only memory with electric field decreasing controller. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, March 8, 1994: US05293337 (55 worldwide citation)

A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to ...


9
Riichiro Shirota, Masaki Momodomi: NAND-type EEPROM having bit lines and source lines commonly coupled through enhancement and depletion transistors. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, November 21, 2000: US06151249 (52 worldwide citation)

In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constitute ...


10
Kazunori Ohuchi, Tomoharu Tanaka, Yoshihisa Iwata, Yasuo Itoh, Masaki Momodomi, Fujio Masuoka: Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, November 3, 1998: US05831903 (49 worldwide citation)

A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated wit ...