1
Masakazu Shoji: Chipset synchronization arrangement. AT&T Bell Laboratories, Herbert M Shapiro, April 30, 1985: US04514647 (58 worldwide citation)

Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp which compares the output of an int ...


2
Masakazu Shoji: Integrated circuits which compensate for local conditions. AT&T Bell Laboratories, Gordon E Nelson, May 26, 1992: US05117130 (43 worldwide citation)

Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the integrated circuit which is subject to the local condition and produces a response to the local condition which ...


3
Masakazu Shoji: VLSI Chip with ground shielding. AT&T Bell Laboratories, Herbert M Shapiro, April 30, 1985: US04514749 (38 worldwide citation)

In VLSI chips, clock pulse skew is increasingly forbidding as one micron technology and operation at 25 megahertz is approached. Skew is avoided by encompassing the clock distribution line in such chips with ground lines to shield the distribution line from capacitive coupling to adjacent control li ...


4
Robert H Krambeck, Masakazu Shoji: Skew-free clock circuit for integrated circuit chip. AT&T Bell Laboratories, Herbert M Shapiro, October 23, 1984: US04479216 (37 worldwide citation)

An op-amp feedback arrangement is used to provide non-skewed clock pulses from a source of skewed clock pulses. Any skew in the clock-in pulses results in a change in the average voltage of a clock-out pulse at the output of the arrangement. The average voltage of the clock-out pulse is compared to ...


5
Masakazu Shoji: Integrated circuit memory device. AT&T, March 12, 1996: US05499208 (34 worldwide citation)

The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, one signal per o ...


6
Masakazu Shoji: Process-tolerant integrated circuit design. Agere Systems, Ryan Mason & Lewis, December 17, 2002: US06496056 (32 worldwide citation)

An operating parameter of an integrated circuit is made substantially insensitive to process variations by configuring the circuit such that an environmental parameter, e.g., supply voltage to a portion of the circuit, is made a function of one or more process parameters, e.g., conduction threshold ...


7
Frank E Barber, Masakazu Shoji: CMOS Integrated circuit digital crossbar switching arrangement. American Telephone and Telegraph Company AT&T Bell Laboratories, David I Caplan, July 18, 1989: US04849751 (28 worldwide citation)

A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the f ...


8
Masakazu Shoji: Dual domino CMOS logic circuit, including complementary vectorization and integration. American Telephone and Telegraph Company AT&T Bell Laboratories, David I Caplan, December 1, 1987: US04710650 (26 worldwide citation)

At each stage of a domino CMOS logic circuit, the output signal S and its inversion S are separately generated in mutually complementary first and second logic networks. These outputs S and S are then used as inputs for succeeding domino logic stages. In this way, both S and S are guaranteed to be l ...


9
Masakazu Shoji: Databus coupling arrangement using transistors of complementary conductivity type. AT&T Bell Laboratories, Arthur J Torsiglieri, December 11, 1984: US04488066 (25 worldwide citation)

To improve the speed of transfer of information to the databus in data processing apparatus, the bus is periodically precharged and the coupling to the databus is by way of a special clocked CMOS buffer circuit.


10
Masakazu Shoji: Optimized low voltage CMOS operation. Agere Systems Guardian Corporation, Istrate Iomescu Jumbepatent com, September 4, 2001: US06285247 (18 worldwide citation)

Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors hav ...