1
Jeffrey W Lutze, Jian Chen, Yan Li, Masaaki Higashitani: Source side self boosting technique for non-volatile memory. SanDisk Corporation, Vierra Magen Marcus Harmon & DeNiro, February 22, 2005: US06859397 (258 worldwide citation)

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the ...


2
Richard M Fastow, Shane C Hollmer, Pau Ling Chen, Michael Van Buskirk, Masaaki Higashitani: Sidewall NROM and method of manufacture thereof for non-volatile memory cells. Advanced Micro Devices, Fujitsu, June 24, 2003: US06583479 (48 worldwide citation)

An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and there ...


3
Jeffrey W Lutze, Jian Chen, Yan Li, Masaaki Higashitani: Source side self boosting technique for non-volatile memory. Sandisk Corporation, Vierra Magen Marcus Harmon & DeNiro, December 13, 2005: US06975537 (45 worldwide citation)

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the ...


4
Masaaki Higashitani: Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells. SanDisk Corporation, Vierra Magen Marcus & DeNiro, September 30, 2008: US07430138 (30 worldwide citation)

Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for ca ...


5
Jun Wan, Jeffrey Lutze, Masaaki Higashitani, Gerrit Jan Hemink, Ken Oowada, Jian Chen, Geoffrey S Gongwer: Selective application of program inhibit schemes in non-volatile memory. SanDisk Corporation, Vierra Magen Marcus & DeNiro, November 13, 2007: US07295478 (30 worldwide citation)

A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program ...


6
Masaaki Higashitani: Flash devices with shared word lines. SanDisk Corporation, Vierra Magen Marcus & DeNiro, February 24, 2009: US07495294 (30 worldwide citation)

Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate ...


7
Masaaki Higashitani, Masatomo Hasegawa: Semiconductor memory of xN type having error correcting circuit by parity. Fujitsu, Nikaido Marmelstein Murray & Oram, September 23, 1997: US05671239 (29 worldwide citation)

A memory device for storing data of a multi-bit structure in a plurality of memory cell blocks has a parity cell block having the same structure as the memory cell block. If read data contains an error bit, this error bit is corrected by an EOR calculation of correct bits and a parity bit. The addre ...


8
Mohan V Dunga, Masaaki Higashitani: Data state-based temperature compensation during sensing in non-volatile memory. Sandisk Corporation, Vierra Magen Marcus & DeNiro, July 13, 2010: US07755946 (27 worldwide citation)

Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A different sense current is provided for each data state, so that a common temperature coefficient is realiz ...


9
Takashi Orimoto, George Matamis, James Kai, Tuan Pham, Masaaki Higashitani, Henry Chien: Methods of forming integrated circuit devices using composite spacer structures. SanDisk Corporation, Vierra Magen Marcus & DeNiro, September 14, 2010: US07795080 (27 worldwide citation)

Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first l ...


10
Jian Chen, Masaaki Higashitani: Use of voids between elements in semiconductor structures for isolation. SanDisk Corporation, Parsons Hsue & de Runtz, May 16, 2006: US07045849 (26 worldwide citation)

A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occu ...