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Bryan P Black, Marvin A Denman: Data processor with branch target address cache and method of operation. Motorola, Lee E Chastain, June 25, 1996: US05530825 (62 worldwide citation)

A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution ad ...


2
Jeffrey Pidge Rupley II, Marvin A Denman, Bradley G Burgess, David C Holloway: Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers. Motorola, December 5, 2000: US06157998 (45 worldwide citation)

A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) b ...


3
Bryan P Black, Marvin A Denman Jr, Seungyoon Peter Song: Data processor with branch target address cache and method of operation. Motorola, September 8, 1998: US05805877 (40 worldwide citation)

A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts ...


4
Mitchell Alsup, Yoav Talgam, Marvin A Denman: Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic. Motorola, Robert L King, January 9, 1990: US04893267 (36 worldwide citation)

In a data processor having an integer arithmetic unit, the carry-in control logic, carry-out control logic, and the overflow control logic of the arithmetic unit are adapted to be directly controlled by respective carry-in enable, carry-out enable, and overflow enable fields of the integer arithmeti ...


5
Yoav Talgam, Mitch K Alsup, Marvin A Denman: Method and apparatus for handling out of order exceptions in a pipelined data unit. Motorola, Robert L King, February 20, 1990: US04903264 (29 worldwide citation)

A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechani ...


6
Marvin A Denman Jr, John M Young, Mitch K Alsup: Circuit and method for accumulating partial products of a single, double or mixed precision multiplication. Motorola, Robert L King, January 9, 1990: US04893268 (26 worldwide citation)

A circuit for use in conjunction with a multiplier receives a portion of completed product bits and a portion of sum and carry bits which, when accumulated, provide a complete output product operand. The circuit is adaptable for use with input operands having single or double precision data formats. ...


7
Marvin A Denman Jr: Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits. Motorola, Lee E Chastain, February 20, 1996: US05493669 (15 worldwide citation)

A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffer periodically receives and stores the result ...


8
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell A Reininger: Method and system for recoding noneffective instructions within a data processing system. International Business Machines Corporation, Michael A Davis Jr, Andrew J Dillon, April 8, 1997: US05619408 (14 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...


9
Marvin A Denman, Artie A Pennington, Seungyoon P Song: System for speculatively executing instructions wherein mispredicted instruction is executed prior to completion of branch processing. International Business Machines Corporation, Motorola, Michael A Davis Jr, June 4, 1996: US05524224 (13 worldwide citation)

A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction prior to execution of the branch instruction. In response to execution of the branch instruction, a seco ...


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