1
Ralf Henninger, Franz Hirler, Joachim Krumrey, Markus Zundel, Walter Rieger, Martin Pölzl: Semiconductor component with an increased breakdown voltage in the edge area. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, October 19, 2004: US06806533 (66 worldwide citation)

A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate ...


2
Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Pölzl, Heimo Hofer: Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration. Infineon Technologies, Laurence A Grenberg, Werner H Stemer, Gregory L Mayback, February 28, 2006: US07005351 (62 worldwide citation)

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in eac ...


3
Joachim Krumrey, Franz Hirler, Ralf Henninger, Martin Pölzl, Walter Rieger: Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, May 10, 2005: US06891223 (33 worldwide citation)

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inact ...


4
Manfred Kotek, Oliver Häberlen, Martin Pölzl, Walter Rieger: Power transistor arrangement and method for fabricating it. Infineon Technologies, Maginot Moore & Beck, July 31, 2007: US07250343 (27 worldwide citation)

In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has ...


5
Martin Pölzl, Franz Hirler, Oliver Häberlen, Manfred Kotek, Walter Rieger: Power transistor arrangement and method for fabricating it. Infineon Technologies, Maginot Moore & Beck, March 6, 2007: US07186618 (18 worldwide citation)

When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode ...


6
Ralf Henninger, Franz Hirler, Martin Pölzl, Walter Rieger: Field-effect-controllable semiconductor component and method for fabricating the component. Infineon Technologies, Lawrence A Greenberg, Werner H Stemer, Ralph E Locher, August 9, 2005: US06927101 (4 worldwide citation)

A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zon ...


7
Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer: Power transistor with at least partially integrated driver stage. Infineon Technologies Austria, Murphy Bilak & Homiller PLLC, May 22, 2018: US09978862

A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of ...


8
Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler: Electronic circuit having adjustable transistor device. Infineon Technologies Austria, Murphy Bilak & Homiller PLLC, August 30, 2016: US09431392

A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate ...