1
Martin J Schwartz, Robert D Becker: Multi-processor system with cache memories. Wang Laboratories, Michael H Shanahan, July 3, 1990: US04939641 (79 worldwide citation)

A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memory means. One status indication tells whether ...


2
Martin J Schwartz, H Frank Howes, Richard J Edry: Byte addressable memory for variable length instructions and data. Raytheon Company, Walter F Dawson, Richard M Sharkansky, March 31, 1987: US04654781 (76 worldwide citation)

A random access memory having the capability to access one or more bytes in one or more memory word locations of a multi-byte memory array within one memory cycle. Variable length instruction and data words composed of multiple bytes are stored in a block of addressable locations in a memory so that ...


3
Robert D Becker, Martin J Schwartz, Kevin H Curcuru, Kenneth J Eng: Memory control unit with selective execution of queued read and write requests. Wang Laboratories, Kenneth L Milik, January 3, 1995: US05379379 (65 worldwide citation)

A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write req ...


4
Martin J Schwartz, Robert D Becker: Multi-processor system with cache memories. Wang Laboratories, Michael H Shanahan, March 17, 1992: US05097409 (58 worldwide citation)

A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit stored within the cache memory. One status indication indicates whether the contents of a storage position have been modified (dirty) since t ...


5
John A Saba, Martin J Schwartz, Richard Tank Kong: CPU having pipelined instruction unit and effective address calculation unit with retained virtual address capability. Wang Laboratories, Kenneth L Milik, April 4, 1995: US05404467 (37 worldwide citation)

A prefetch unit includes a Branch history table for providing an indication of an occurrence of a Branch instruction having a Target Address that was previously taken. A plurality of Branch mark bits are stored in an instruction queue, on a half word basis, in conjunction with a double word of instr ...


6
Richard F Giunta, Robert D Becker, Martin J Schwartz, Richard W Coyle, Kevin H Curcuru: Memory diagnostic apparatus and method. Wang Laboratories, Michael H Shanahan, Gordon E Nelson, July 24, 1990: US04943966 (33 worldwide citation)

A system console 30 is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays 16-22. The information read from the memory boards is indicative at least of which of the memory arrays has malfunction ...


7
Martin J Schwartz, Gerald F Muething Jr: Tester with fast refire recovery time. Teradyne, Edmund J Walsh, December 29, 1998: US05854797 (22 worldwide citation)

Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signal are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circu ...


8
Robert D Becker, Martin J Schwartz, Kevin H Curcuru: System bus having multiplexed command/ID and data. Wang Laboratories, David N Caracappa, Kenneth L Milik, August 10, 1993: US05235684 (19 worldwide citation)

A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the ...


9
Anthony S Fong, Robert D Becker, Martin J Schwartz, Janis Delmonte: Apparatus and method for executing a conditional branch instruction. Wang Laboratories, Michael H Shanahan, July 23, 1991: US05034880 (9 worldwide citation)

Apparatus for executing a conditional branch instruction in a pipelined processing unit which has an instruction queue for storing an instruction stream, address generating apparatus connected to the head of the instruction queue for generating and retaining an address defined in the portion of the ...


10
Martin J Schwartz, Gerald F Muething Jr: Tester with fast refire recovery time. Teradyne, li hui, September 13, 2000: CN98808025

Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signals are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circ ...