1
Martin H Manley: Buried bit-line source-side injection flash memory cell. National Semiconductor Corporation, Limbach & Limbach, February 8, 1994: US05284784 (84 worldwide citation)

The present invention provides a flash EPROM cell structure that has the advantages of source-side injection, but which is formed in such a way as to allow it to be utilized in a virtual-ground buried bit-line array layout. The buried bit-line array confers two advantages over the more conventional ...


2
Martin H Manley: Manufacture of a split-gate EPROM cell using polysilicon spacers. National Semiconductor Corporation, Limbach Limbach & Sutton, November 5, 1991: US05063172 (54 worldwide citation)

The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit pro ...


3
Harlan Lee Sur Jr, Subhas Bothra, Xi Wei Lin, Martin H Manley, Robert Payne: Low power programmable fuse structures. VLSI Technology, Hickman & Martine, December 29, 1998: US05854510 (52 worldwide citation)

Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide regi ...


4
Martin H Manley, Michael J Hart, Philip J Cacharelis: Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region. National Semiconductor, Steven F Caserza, Irv Rappaport, April 28, 1992: US05108939 (44 worldwide citation)

A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the g ...


5
Harlan Lee Sur Jr, Subhas Bothra, Xi Wei Lin, Martin H Manley, Robert Payne: Low power programmable fuse structures and methods for making the same. VLSI Technology, Hickman & Martine, March 16, 1999: US05882998 (40 worldwide citation)

Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide regi ...


6
Martin H Manley: Split-gate EPROM cell using polysilicon spacers. National Semiconductor Corporation, Limbach & Limbach, May 19, 1992: US05115288 (40 worldwide citation)

The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit pro ...


7
Vijay Parthasarathy, Martin H Manley: Gate pullback at ends of high-voltage vertical transistor structure. Power Integrations, The Law Offices of Bradley J Bereznak, September 29, 2009: US07595523 (33 worldwide citation)

In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions ...


8
Martin H Manley: EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region. National Semiconductor Corporation, Limbach & Limbach, April 4, 1995: US05404037 (28 worldwide citation)

A method of semiconductor fabrication, in which a single aperture is used to define both a thin oxide tunneling region and a drain diffusion region in a self-aligned fashion, produces a device structure suitable for use in an electrically-erasableread-only memory (EEPROM) cell. A gate oxide is grown ...


9
Vijay Parthasarathy, Sujit Banerjee, Martin H Manley: Checkerboarded high-voltage vertical transistor layout. Power Integrations, The Law Offices of Bradley J Bereznak, December 28, 2010: US07859037 (17 worldwide citation)

In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the tran ...


10
Vijay Parthasarathy, Sujit Banerjee, Martin H Manley: Checkerboarded high-voltage vertical transistor layout. Power Integrations, The Law Offices of Bradley J Bereznak, September 20, 2011: US08022456 (16 worldwide citation)

In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the tra ...