1
Mark S Isfeld, Tracy D Mallory, Bruce W Mitchell, Michael J Seaman, Nagaraj Arunkumar: Bridge/router architecture for high performance scalable networking. 3Com Corporation, Wilson Sonsini Goodrich & Rosati, September 1, 1998: US05802278 (292 worldwide citation)

A high performance scalable networking bridge/router system is based on a backbone communication medium and message passing process which interconnects a plurality of input/output modules. The input/output modules vary in complexity from a simple network interface device having no switching or routi ...


2
Mark S Isfeld, Bruce W Mitchell, Michael J Seaman, Tracy D Mallory, Nagaraj Arunkumar: Network intermediate system with message passing architecture. 3Com Corporation, Wilson Sonsini Goodrich & Rosati, January 7, 1997: US05592622 (189 worldwide citation)

A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which ori ...


3
Mark S Isfeld, Tracy D Mallory, Bruce W Mitchell, Michael J Seaman, Nagaraj Arunkumar, Pyda Srisuresh: High throughput message passing process using latency and reliability classes. 3Com Corporation, Mark A Wilson Sonsini Goodrich & Rosati Haynes, October 27, 1998: US05828835 (180 worldwide citation)

A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. O ...


4
Mark S Isfeld, Bruce W Mitchell: System for managing data flow among devices by storing data and structures needed by the devices and transferring configuration information from processor to the devices. 3Com Corporation, Haynes & Davis, January 9, 1996: US05483640 (82 worldwide citation)

An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface ...


5
John H Hughes, Mark S Isfeld: High performance shared memory for a bridge router supporting cache coherency. 3Com Corporation, Wilson Sonsini Goodrich & Rosati, January 25, 2000: US06018763 (44 worldwide citation)

An internetwork device manages the flow of packets of I/O data among a plurality of network interface devices. The internetwork device includes an I/O bus which is coupled to the plurality of network interface devices and a shared memory, for storing packets of I/O data and control structures needed ...


6
Mark S Isfeld: System for classifying input/output events for processes servicing the events. 3Com Corporation, Haynes & Davis, November 28, 1995: US05471618 (28 worldwide citation)

A mixed poll-interrupt system optimizes performance of a processor managing status information indicating the occurrence of service-requiring events generated by I/O devices. Separation logic separates the status information into a first class of more time-critical status indications and a second cl ...


7
Mark S Isfeld, Michael H Bowman, Niles E Strohl: Input/output bus architecture with parallel arbitration. 3Com Corporation, Haynes & Davis, October 17, 1995: US05459840 (26 worldwide citation)

A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the ...


8
Bruce W Mitchell, Mark S Isfeld: Driver for tri-state bus. 3COM Corporation, Wilson Sonsini Goodrich & Rosati, July 8, 1997: US05646553 (16 worldwide citation)

A tri-state synchronous bus driver avoids contention between succeeding cycles by shutting off each device's output enable early, so that it is guaranteed to no longer drive the line by the time any other device begins to drive. Enable activation occurs on a leading edge of the bus clock, and deacti ...


9
Mark S Isfeld: System for generating a variable signal in response to a toggle signal selectively delayed using a clock edge and time delay measured from the clock edge. 3ComCorporation, September 2, 1997: US05664166 (7 worldwide citation)

A digital circuit for generating a signal with a pulse width that is other than a half multiple of the clock is shown. The signal width can be greater or less than the clock period. This digital circuit includes a signal modifier, responsive to the clock signal, for generating a signal with a logic ...