1
Mark S Ebel: High speed eprom cell and array. Silicon Macrosystems Incorporated, Flehr Hohbach Test Albritton & Herbert, May 5, 1987: US04663740 (24 worldwide citation)

A high speed EPROM cell comprises two floating gate field effect transistors and one field effect transistor. One of the floating gate transistors is smaller than the other floating gate transistor and functions as a programming transistor in developing charge on the interconnected floating gates. T ...


2
Giora Yaron, Ying K Shum, Ury Priel, Jayasimha S Prasad, Mark S Ebel: Electrically programmable and erasable memory cell. National Semiconductor Corporation, Paul J Winters, Gail W Woodward, Michael J Pollock, October 16, 1984: US04477825 (22 worldwide citation)

An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain reg ...


3
Ury Priel, Giora Yaron, Mark S Ebel: Memory core testing system. National Semiconductor Corporation, Michael J Pollock, Paul J Winters, Gail W Woodward, May 21, 1985: US04519076 (17 worldwide citation)

A means for testing the threshold voltage changes in a programmable and erasable floating gate memory cell by accessing directly and exclusively the cells in the core, and the amplifiers that sense the operation of the cells, so as to measure the relative currents therein as an indication of thresho ...


4
John Gionis, Mark S Ebel, William M Regitz: High speed ECL compatible MOS-Ram. Intel Corporation, Spensley Horn & Lubitz, February 10, 1976: US03938109 (16 worldwide citation)

A metal-oxide-silicon (MOS), random-access memory (RAM) which is emitter-coupled logic (ECL) compatible and which does not require any high level clock inputs. The memory utilizes pseudo-static cells which are refreshed with an asynchronous charge-pump signal generated on the memory chip. Buffers ut ...


5
Mark S Ebel: Semiconductor memory core program control circuit. National Semiconductor Corporation, Michael J Pollock, Paul J Winters, Gail W Woodward, April 3, 1984: US04441172 (10 worldwide citation)

A circuit to restrain the rise time of a programming pulse generated in an electrically alterable read-only semiconductor memory in which excessively sudden changes in the pulse are capacitively coupled, through active devices that can be built on the chip, to a grounding switch device so as to peri ...


6
Mark S Ebel: Low voltage and low power static random access memory (SRAM). Enable Semiconductor, Carr & Ferrell, December 12, 2000: US06160733 (9 worldwide citation)

A static random access memory having a static random access memory cell array, row address buffers for receiving row address signals, and column address buffers for receiving column address signals. The static random access memory also includes a clock chain circuit connected to the row address buff ...


7
Mark S Ebel, Robert Shen: Voltage source and memory-voltage switch in a memory chip. Enable Semiconductor, Carr & Ferrell, November 24, 1998: US05841724 (8 worldwide citation)

A circuit for connecting a memory cell matrix to voltage sources includes a voltage sensor responsive to the voltage levels of a first voltage source and of a second voltage source by producing a sense signal, and a voltage source coupler connected between the memory cell matrix and the voltage sens ...


8
Mark S Ebel, Michael R McCoy: Method of storing data in a read only memory to enhance access time. Chipware, International Microelectronic Products, Henry K Woodward, September 3, 1991: US05046045 (5 worldwide citation)

The access time in reading data from a read only memory is enhanced by selectively inverting data stored in the memory. Each storage location along a wordline is weighted according to the distance of the bit location from the wordline driver, and bits stored therein are weighted by the bit location ...


9
Ury Priel, Giora Yaron, Mark S Ebel: Semiconductor memory byte clear circuit. National Semiconductor Corporation, Michael J Pollock, Paul J Winters, Gail W Woodward, April 10, 1984: US04442510 (3 worldwide citation)

A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the se ...


10
Mark S Ebel: Semiconductor memory core programming circuit. National Semiconductor Corporation, Michael J Pollock, Paul J Winters, Gail W Woodward, April 24, 1984: US04445205 (2 worldwide citation)

A programming pulse generating circuit, suitable for use on an electrically alterable read-only semiconductor memory, that decouples from the high voltage supply when in a standby condition so as to not draw current from the supply. Alternative voltage supply connections are effected by depletion mo ...