1
Michael Farmwald, Mark Horowitz: Apparatus for synchronously generating clock signals in a data processing system. Rambus, Blakely Sokoloff Taylor & Zafman, September 7, 1993: US05243703 (374 worldwide citation)

An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its f ...


2
Michael Farmwald, Mark Horowitz: Integrated circuit I/O using high performance bus interface. Rambus, Blakely Sokoloff Taylor & Zafman, June 7, 1994: US05319755 (277 worldwide citation)

An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecti ...


3
Michael Farmwald, Mark Horowitz: Memory circuitry having bus interface for receiving information in packets and access time registers. Rambus, Blakeley Sokoloff Taylor & Zafman, February 25, 1997: US05606717 (258 worldwide citation)

An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a pluralit ...


4
Michael Farmwald, Mark Horowitz: Memory module having memory devices containing internal device ID registers and method of initializing same. Rambus, Steinberg & Whitt, July 27, 1999: US05928343 (250 worldwide citation)

A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a ...


5
Michael Farmwald, Mark Horowitz: Integrated circuit I/O using a high performance bus interface. Rambus, Blakely Sokoloff Taylor & Zafman, April 30, 1996: US05513327 (166 worldwide citation)

A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting ea ...


6
Michael Farmwald, Mark Horowitz: Integrated circuit I/O using a high performance bus interface. Rambus, Blakely Sokoloff Taylor & Zafman, June 10, 1997: US05638334 (158 worldwide citation)

The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for sto ...


7
Bennett Wilburn, Neel Joshi, Marc C Levoy, Mark Horowitz: Apparatus and method for capturing a scene using staggered triggering of dense camera arrays. The Board of Trustees of the Leland Stanford Junior University, Lumen Patent Firm, September 27, 2011: US08027531 (141 worldwide citation)

This invention relates to an apparatus and a method for video capture of a three-dimensional region of interest in a scene using an array of video cameras. The video cameras of the array are positioned for viewing the three-dimensional region of interest in the scene from their respective viewpoints ...


8
Michael Farmwald, Mark Horowitz: Synchronous memory device having an internal register. Rambus, Steinberg & Whitt, September 21, 1999: US05954804 (128 worldwide citation)

The present invention is directed to an integrated circuit device having at least one memory section including a plurality of memory cells. The device includes an internal register to store an identification value which identifies the device on a bus. The device further includes interface circuitry, ...


9
Michael Farmwald, Mark Horowitz: Memory device having write latency. Rambus, Neil A Steinberg, November 6, 2001: US06314051 (126 worldwide citation)

A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal t ...


10
Michael Farmwald, Mark Horowitz: Method of operating a synchronous memory device. Rambus, Neil A Steinberg, August 8, 2000: US06101152 (124 worldwide citation)

A synchronous memory device having a plurality of memory cells and a method of operation thereof. The memory device comprising: receiver circuitry to receive a first external clock signal; and output driver circuitry, to output data after a preprogrammed number of clock cycles of the first external ...