Shivaling S Mahant Shetti, Mark G Harward: Memory cell circuit and operation thereof. Texas Instruments Incorporated, Douglas A Sorensen, James T Comfort, Melvin Sharp, November 26, 1991: US05068825 (5 worldwide citation)

An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an ...

Shivaling S Mahant Shetti, Manisha Agarwala, Mahesh M Mehendale, Robert J Landers, Mark G Harward: Adder-based base cell for field programmable gate arrays. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, January 30, 1996: US05488315 (4 worldwide citation)

An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 ...

Mark G Harward: Programmable logic device routing architecture. Texas Instruments Incorporated, John D Crane, Richard L Donaldson, November 21, 1995: US05469078 (3 worldwide citation)

An integrated electronic circuit architecture has low leakage current and capacitance and includes a user-programmable integrated circuit design (110) having a plurality of designed conductors (112, 118) and a plurality of designed functional circuit blocks (e.g., 12,14, etc.). In the architecture, ...

Shivaling S Mahant Shetti, Mark G Harward, Lawrence A Arledge Jr, Ravishankar Sundaresan: CMOS with parasitic bipolar transistor. Texas Instruments Incorporated, Peter T Rutkowski, Richard L Donaldson, William E Hiller, March 3, 1998: US05723988 (1 worldwide citation)

A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.