1
Donald R Banks, Ronald G Pofahl, Mark F Sylvester, William G Petefish, Paul J Fischer: Method for assembling an integrated circuit chip package having an underfill material between a chip and a substrate. Gore Enterprise Holdings, Victor M Genco Jr, January 18, 2000: US06015722 (56 worldwide citation)

The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integ ...


2
Mark F Sylvester, David A Hanson, William G Petefish: Interconnect module with reduced power distribution impedance. 3M Innovative Properties Company, Melanie G Gover, January 25, 2005: US06847527 (45 worldwide citation)

An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated cir ...


3
Donald R Banks, Ronald G Pofahl, Mark F Sylvester, William G Petefish, Paul J Fischer: Method for assembling an integrated circuit chip package having at least one semiconductor device. Gore Enterprise Holdings, Victor M Genco Jr, July 6, 1999: US05919329 (38 worldwide citation)

The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integ ...


4
Mark F Sylvester: Chip package mounting structure for controlling warp of electronic assemblies due to thermal expansion effects. W L Gore & Associates, Victor M Genco Jr, January 11, 2000: US06014317 (31 worldwide citation)

A chip package is provided for controlling warp of electronic assemblies. The chip package has a first component mounted on one side of a substrate. The substrate is a multi-layered laminate having a plurality of dielectric layers made of an organic material. The first component has a different coef ...


5
Mark F Sylvester, William George Petefish, Paul J Fischer: Method for minimizing warp and die stress in the production of an electronic assembly. W L Gore & Associates, Victor M Genco Jr, February 9, 1999: US05868887 (30 worldwide citation)

A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coeffic ...


6
Paul J Fischer, Robin E Gorrell, Mark F Sylvester: Dimensionally stable core for use in high density chip packages. W L Gore & Associates, Victor M Genco Jr, December 8, 1998: US05847327 (29 worldwide citation)

A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on ...


7
Mark F Sylvester: Method of increasing package reliability using package lids with plane CTE gradients. W L Gore & Associates, Victor M Genco Jr, November 17, 1998: US05838063 (25 worldwide citation)

A lid for a chip/package system includes a body sized to fit over an integrated circuit chip and being connectable to a package. The body has at least two regions exhibiting different coefficients of thermal expansion, with one CTE matching that of the chip and the other matching that of the package ...


8
Mark F Sylvester: Integrated circuit chip package assembly. W L Gore & Associates, Victor M Genco Jr, May 4, 1999: US05900312 (21 worldwide citation)

A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrat ...


9
W David Smith, John A Olenick, Carlos L Barton, Jane L Cercena, Daniel J Navarro, Kathleen R Olenick, Angela M Kneeland, Thomas S Kneeland, Mark F Sylvester, Curtis H Kempton, Scott E Derosier, Lynn E Burdick, Richard T Traskos, Robert B Huntington, James S Rivers, Samuel Gazit, Jeffrey B Ott, William P Harper: Method of manufacture multichip module substrate. Rogers Corporation, Fishman Dionne & Cantor, February 22, 1994: US05287619 (20 worldwide citation)

In accordance with the present invention, an MCM substrate product is manufactured in an additive process using multiple layers of a fluoropolymer composite material and copper. The copper layers are plated, and the fluoropolymer composite layers are laminated. A seeding process promotes reliable bo ...


10
Mark F Sylvester, David B Noddin: Method of increasing package reliability by designing in plane CTE gradients. W L Gore & Associates, Victor M Genco Jr, October 3, 2000: US06127250 (19 worldwide citation)

A method of manufacturing a multi-layered structure includes forming first and second layers, patterning the first layer, determining a distribution of material in at least one area of the first layer, and altering the material content of one of the first and second layers in at least one of the fir ...