21
Toshiharu Furukawa, Mark C Hakey, David V Horak, William H Ma, Jack A Mandelman: Five square vertical dynamic random access memory cell. International Business Machines Corporation, Howard J Walter Jr, Whitham Curtis & Whitham, September 7, 1999: US05949700 (28 worldwide citation)

Five square dynamic random access memory (DRAM) cell is prepared with a vertical transfer device with long channel length. In this construction, channel length is not affected by cell size scaling requirements.


22
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Process for self-alignment of sub-critical contacts to wiring. International Business Machines Corporation, John J Goodwin, October 16, 2001: US06303272 (27 worldwide citation)

A method for forming contacts on an integrated circuit that are self-aligned with the wiring patterns of the integrated circuit. In the method a thicker lower layer of a first material and a thinner upper layer of a second material are formed on a substrate. The features of the metal wiring is patte ...


23
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David Horak, William H Ma, James M Never: Method for a controlled bottle trench for a dram storage node. International Business Machines Corporation, Robert Curcio, Eugene I Shkurko, DeLio & Peterson, February 20, 2001: US06190988 (25 worldwide citation)

A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the s ...


24
Steven J Holmes, Charles Black, David J Frank, Toshiharu Furukawa, Mark C Hakey, David V Horak, William Hsioh Lien Ma, Keith R Milkove, Kathryn W Guarini: Method for increasing the capacitance of a semiconductor capacitors. International Business Machines Corporation, Mark F Chadurjian, Cantor Colburn, March 19, 2002: US06358813 (25 worldwide citation)

Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode patt ...


25
Toshiharu Furukawa, David V Horak, Steven J Holmes, Mark C Hakey, Jack A Mandelman: Dram cell with three-sided-gate transfer device. International Business Machines Corporation, William D Sabo, Ratner & Prestia, September 19, 2000: US06121651 (23 worldwide citation)

A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a f ...


26
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Method for forming features using frequency doubling hybrid resist and device formed thereby. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, December 28, 1999: US06007968 (21 worldwide citation)

The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the "loops" formed by the hybrid resist. This allows the method ...


27
Toshijaru Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III, Chung H Lam, Gerhard I Meijer: Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells. International Business Machines Corporation, Gibb & Rahman, Ido Tuchman Esq, August 14, 2007: US07256415 (21 worldwide citation)

Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially ā€œUā€ shaped. The double memory cells comprise two essentially ā€œUā€ shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer san ...


28
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Method for forming borderless gate structures and apparatus formed thereby. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, March 27, 2001: US06207514 (21 worldwide citation)

A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective ...


29
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III, Peter H Mitchell, Larry A Nesbit, James A Slinkman: Sub-lithographic imaging techniques and processes. International Business Machines Corporation, Richard Kotulak, Greenblum & Bernstein, September 8, 2009: US07585614 (21 worldwide citation)

A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge durin ...


30
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Borderless gate structures. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, March 11, 2003: US06531724 (21 worldwide citation)

A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective ...