1
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandelman, William R Tonti: SOI stacked DRAM logic. International Business Machines Corporation, Mark F Chadurjian, Whitman Curtis & Christofferson P C, April 8, 2003: US06544837 (206 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...


2
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III: Accessible chip stack and process of manufacturing thereof. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, May 5, 2009: US07528494 (174 worldwide citation)

A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip de ...


3
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Method for forming pillar memory cells and device formed thereby. International Business Machines Corporation, Eugene I Shkurko, Schmeiser Olsen & Watts, August 1, 2000: US06096598 (137 worldwide citation)

The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form s ...


4
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandclman, William R Tonti: SIO stacked DRAM logic. International Business Machines Corporation, Mark F Chadurjian, Whitham Curtis & Christofferson P C, July 8, 2003: US06590258 (130 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...


5
Toshiharu Furukawa, Mark C Hakey, David V Horak, William H Ma, Jack A Mandelman: Trench storage dynamic random access memory cell with vertical transfer device. International Business Machines Corporation, Howrd J Walter Esq, McGuireWoods, May 1, 2001: US06225158 (125 worldwide citation)

A trench storage dynamic random access memory cell with vertical transfer device can be formed in a wafer having prepared shallow trench isolation. Vertical transfer device is built as the deep trenches are formed. Using square printing to form shallow trench isolation and deep trenches, allows for ...


6
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Howard L Kalter, Jack A Mandelman, Paul A Rabidoux, Jeffrey J Welser: Structure for folded architecture pillar memory cell. International Business Machines Corporation, Mark F Chadurjian, Scully Scott Murphy & Presser, August 27, 2002: US06440801 (107 worldwide citation)

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are ...


7
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III: Field effect transistor. International Business Machines Corporation, Schmeiser Olsen & Watts, Richard M Kotulak, August 23, 2011: US08004024 (89 worldwide citation)

A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions ...


8
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Methods of T-gate fabrication using a hybrid resist. International Business Machines Corporation, Kelly M Reynolds, Mark F Chadurjian, DeLio & Peterson, May 14, 2002: US06387783 (76 worldwide citation)

Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask havi ...


9
Kuang Jung R Chen, Mark C Hakey, Steven J Holmes, Wu Song Huang, Paul A Rabidoux: Hybrid resist based on photo acid/photo base blending. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, January 15, 2002: US06338934 (71 worldwide citation)

A photo resist composition contains a polymer resin, a first photo acid generator (PAG) requiring a first dose of actinic energy to generate a first photo acid, and a photo base generator (PBG) requiring a second dose of actinic energy, different from the first dose, to generate a photo base. The am ...


10
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Howard L Kalter, Jack A Mandelman, Paul A Rabidoux, Jeffrey J Welser: Structure for folded architecture pillar memory cell. International Business Machines Corporation, Eugene I Shkurko Esq, Scully Scott Murphy & Presser, September 5, 2000: US06114725 (66 worldwide citation)

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are f ...