Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi Chang Miao, Christopher D Metcalf, Bruce Edwards, Carl G Ramey, Mark B Rosenbluth, David M Wentzlaff, Christopher J Jackson, Ben Harrison, Kenneth M Steele, John Amann, Shane Bell, Richard Conlin, Kevin Joyce, Christine Deignan, Liewei Bao, Matthew Mattina, Ian Rudolf Bratt, Richard Schooler: Computing in parallel processing environments. Tilera Corporation, Fish & Richardson P C, May 27, 2014: US08738860 (109 worldwide citation)

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from ot ...

Mark B Rosenbluth, Gilbert Wolrich, Debra Bernstein: Software controlled content addressable memory in a general purpose execution datapath. Intel Corporation, Fish & Richardson P C, March 15, 2005: US06868476 (73 worldwide citation)

A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.

Mark B Rosenbluth, Gilbert Wolrich, Debra Bernstein: Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment. Intel Corporation, Fish & Richardson P C, May 8, 2007: US07216204 (59 worldwide citation)

Stored units of information related to packet processing are associated with identifiers, each of which is maintained as an entry in a Content Addressable Memory (CAM). Each entry includes status information associated with the information unit with which the identifier is associated. The status inf ...

Hugh M Wilkinson III, Matthew J Adiletta, Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Myles J Wilde: Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section. Intel Corporation, Fish & Richardson P C, August 23, 2005: US06934951 (35 worldwide citation)

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engine ...

Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein: Enqueue operations for multi-buffer packets. Intel Corporation, Fish & Richardson P C, August 17, 2004: US06779084 (27 worldwide citation)

The use of enqueue operations to append multi-buffer packets to the end of a queue includes receiving a request to place a string of linked buffers in a queue, specifying a first buffer in the string and a queue descriptor associated with the first buffer in the string, updating the buffer descripto ...

Mason B Cabot, Frank T Hady, Mark B Rosenbluth: Method of implementing off-chip cache memory in dual-use SRAM memory for network processors. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 3, 2007: US07200713 (25 worldwide citation)

A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i.e., conventional SRAM use). The cache regi ...

Mark B Rosenbluth, Xiao Feng Li, Dz ching, Aaron R Kunze: Multiprocessor breakpoint. Intel Corporation, Caven & Aghevli, March 30, 2010: US07689867 (22 worldwide citation)

Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system. For example, a signal may be generated to indicate ...

Donald F Hooper, Mark B Rosenbluth, Gilbert Wolrich, Matthew J Adiletta, Hugh M Wilkinson III, Robert J Kushlis: Processing a data packet. Intel Corporation, Fish & Richardson P C, October 28, 2008: US07443836 (21 worldwide citation)

A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the exe ...

Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Richard Guerin: Command ordering. Intel Corporation, Fish & Richardson PC, May 18, 2004: US06738831 (18 worldwide citation)

A method of ordering commands includes receiving a set of related commands that have a predetermined execution sequence, the commands being received in an arbitrary order that may be different from the execution sequence and releasing a later received command of the set for execution before an earli ...

Donald F Hooper, Eric Walker, Dennis Rivard, Mark B Rosenbluth: Graphical user interface for use during processor simulation. Intel Corporation, Grossman Tucker Perreault & Pfleger PLLC, March 23, 2010: US07684970 (17 worldwide citation)

In accordance with one exemplary embodiment, the present disclosure includes a method for executing application software during a simulation that models a processor for which the application software was developed. The method may include capturing results of the simulation to produce a simulation hi ...