1
James A Gasbarro, Mark A Horowitz, Richard M Barth, Winston K M Lee, Wingyu Leung, Paul M Farmwald: Method and circuitry for minimizing clock-data skew in a bus system. Rambus, Blakely Sokoloff Taylor & Zafman, July 11, 1995: US05432823 (326 worldwide citation)

A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnar ...


2
Mark A Horowitz, James A Gasbarro, Wingyu Leung: Electrical current source circuitry for a bus. Rambus, Blakely Sokoloff Taylor & Zafman, October 19, 1993: US05254883 (320 worldwide citation)

Electrical current source circuitry for a bus is described. The circuitry includes transistor circuitry coupled between the bus and ground for controlling bus current, control circuitry coupled to the transistor circuitry, and a controller coupled to the control circuitry for controlling the transis ...


3
Mark A Horowitz, Winston K M Lee: High speed bus system. Rambus, Blakely Sokoloff Taylor & Zafman, October 11, 1994: US05355391 (299 worldwide citation)

In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is termina ...


4
Jared LeVan Zerbe, Kevin S Donnelly, Stefanos Sidiropoulos, Donald C Stark, Mark A Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W Garlepp, Tsyr Chyang Ho, Benedict Chung Kwong Lau: Bus system optimization. Rambus, Pennie & Edmonds, November 4, 2003: US06643787 (239 worldwide citation)

A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets ...


5
Wingyu Leung, Mark A Horowitz: Method and circuitry for clock synchronization. Rambus, Blakely Sokoloff Taylor & Zafman, January 16, 1996: US05485490 (235 worldwide citation)

Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select sign ...


6
Mark A Horowitz, Richard M Barth, Craig E Hampel, Alfredo Moncayo, Kevin S Donnelly, Jared L Zerbe: Apparatus and method for topography dependent signaling. Rambus, November 20, 2001: US06321282 (223 worldwide citation)

Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topo ...


7
Kevin S Donnelly, Pak Shing Chau, Mark A Horowitz, Thomas H Lee, Mark G Johnson, Benedict C Lau, Leung Yu, Bruno W Garlepp, Yiu Fai Chan, Jun Kim, Chanh Vi Tran, Donald C Stark: Delay-locked loop circuitry for clock delay adjustment. Rambus, Pennie & Edmonds, September 26, 2000: US06125157 (196 worldwide citation)

Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each s ...


8
Marc S Levoy, Yi Ren Ng, Mark A Horowitz: Microscopy arrangements and approaches. The Board of Trustees of the Leland Stanford Junior University, Crawford Maunu PLLC, May 25, 2010: US07723662 (167 worldwide citation)

Light-field microscopy is facilitated using an approach to image computation. In connection with an example embodiment, a subject (e.g., 105) is imaged by passing light from the subject through a microlens array (e.g., 120) to a photosensor array (e.g., 130) to simultaneously detect light from the s ...


9
Kevin S Donnelly, Pak Shing Chau, Mark A Horowitz, Thomas H Lee, Mark G Johnson, Benedict C Lau, Leung Yu, Bruno W Garlepp, Yiu Fai Chan, Jun Kim, Chanh Vi Tran, Donald C Stark, Nhat M Nguyen: Delay locked loop circuitry for clock delay adjustment. Rambus, Pennie & Edmonds, March 25, 2003: US06539072 (141 worldwide citation)

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit del ...


10
Frederick A Ware, James A Gasbarro, John B Dillon, Matthew M Griffin, Richard M Barth, Mark A Horowitz: Method and apparatus for power control in devices. Rambus, Blakely Sokoloff Taylor & Zafman, August 9, 1994: US05337285 (122 worldwide citation)

A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provi ...



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