1
William N Joy, Marc Tremblay, Gary Lauterbach, Joseph I Chamdani: Thread switch logic in a multiple-thread processor. Sun Microsystems, Ken J Koestner, Skjerven Morrill MacPherson, January 22, 2002: US06341347 (212 worldwide citation)

A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L


2
William N Joy, Marc Tremblay, Gary Lauterbach, Joseph I Chamdani: Switching method in a multi-threaded processor. Sun Microsystems, January 14, 2003: US06507862 (104 worldwide citation)

A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded ...


3
Marc Tremblay, James Michael O Connor, William N Joy: Processor with accelerated array access bounds checking. Sun Microsystems, Forrest Gunnison, January 11, 2000: US06014723 (100 worldwide citation)

An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that sto ...


4
Ron Carmel, Hugo J C DesRosiers, Daniel Gomez, James F Kramer, Jerry Tian, Marc Tremblay, Christopher J Ullrich: System, method and data structure for simulated interaction with graphical objects. Immersion Corporation, Thelen Reid & Preist, David B Ritchie, May 23, 2006: US07050955 (93 worldwide citation)

Object simulation and interaction of and between computer-generated or graphical objects in a virtual space includes neutral scene graphs, data structures and procedures for using such graphs and data structures.


5
James Michael O Connor, Marc Tremblay, Sanjay Vishin: Generation isolation system and method for garbage collection. Sun Microsystems, Skjerven Morrill MacPherson Franklin & Friel L, August 1, 2000: US06098089 (92 worldwide citation)

Architectural support for generation isolation is provided through trapping of intergenerational pointer stores. Identification of pointer stores as intergenerational is performed by a store barrier responsive to an intergenerational pointer store trap matrix that is programmably encoded with store ...


6
James Michael O Connor, Marc Tremblay: Instruction folding for a stack-based machine. Sun Microsystems, Skjerven Morrill MacPherson Franklin & Friel, February 15, 2000: US06026485 (87 worldwide citation)

An instruction decoder allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack merely as a precursor to a second JAVA virtual machine instruction which operates on the top of stack operand. Such an instruction decoder identifies foldable instruction se ...


7
Mark S Moir, Maurice P Herlihy, Quinn A Jacobson, Shailender Chaudhry, Marc Tremblay: Method and apparatus for releasing memory locations during transactional execution. Sun Microsystems, Park Vaughan & Fleming, April 17, 2007: US07206903 (84 worldwide citation)

One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution ...


8
James Michael O Connor, Marc Tremblay, Sanjay Vishin: Write barrier system and method for trapping garbage collection page boundary crossing pointer stores. Sun Microsystems, David W O Brien, Skjerven Morrill MacPherson Franklin & Friel, December 1, 1998: US05845298 (76 worldwide citation)

Architectural support is provided for trapping of garbage collection page boundary crossing pointer stores. Identification of pointer stores as boundary crossing is performed by a store barrier responsive to a garbage collection page mask that is programmably encoded to define a garbage collection p ...


9
Marc Tremblay, James Michael O Connor, William N Joy: Hardware virtual machine instruction processor. Sun Microsystems, Forrest Gunnison, February 1, 2000: US06021469 (72 worldwide citation)

A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. ...


10
Marc Tremblay, James Michael O Connor: Processor for executing instruction sets received from a network or from a local memory. Sun Microsystems, Philip J McKay, Forrest Gunnison, July 20, 1999: US05925123 (70 worldwide citation)

A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor in ...