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Manoj Mehrotra, Bantval J Baliga: Schottky barrier rectifier with MOS trench. North Carolina State University, Bell Seltzer Park & Gibson, November 15, 1994: US05365102 (165 worldwide citation)

A trench MOS Schottky barrier rectifier includes a semiconductor substrate having first and second faces, a cathode region of first conductivity type at the first face and a drift region of first conductivity type on the cathode region, extending to the second face. First and second trenches are for ...


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Puneet Kohli, Manoj Mehrotra: Multiple indium implant methods and devices and integrated circuits therefrom. Texas Instruments Incorporated, Warren L Franz, Wade J Brady III, Frederick J Telecky Jr, June 14, 2011: US07960238 (102 worldwide citation)

An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor su ...


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Manoj Mehrotra, Bantval J Baliga: Bidirectional AC switching device with MOS-gated turn-on and turn-off control. North Carolina State University, Bell Seltzer Park & Gibson, February 20, 1996: US05493134 (24 worldwide citation)

A bidirectional semiconductor switching device includes a semiconductor substrate having first and second device terminals on opposite faces thereof, a thyristor in the substrate for providing regenerative conduction in a first direction, between the first device terminal and the second device termi ...


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Manoj Mehrotra, John N Randall, Mark S Rodder: Sub-critical-dimension integrated circuit features. Texas Instruments Incorporated, Peter K McLarty, W James Brady III, Frederick J Telecky Jr, February 3, 2004: US06686300 (14 worldwide citation)

A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (


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Manoj Mehrotra: Dual salicide process for optimum performance. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, January 17, 2006: US06987061 (10 worldwide citation)

The present invention pertains to forming respective silicides on multiple transistors in a single process. High performance is facilitated with simple and highly integrated process flows. As such, transistors, and an integrated circuit containing the transistors, can be fabricated efficiently and a ...


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Manoj Mehrotra, Amitabh Jain: Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, March 18, 2008: US07344929 (8 worldwide citation)

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions ...


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Chimin Hu, Amitabh Jain, Reima Tapani Laaksonen, Manoj Mehrotra: Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, November 19, 2002: US06482688 (7 worldwide citation)

A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silic ...


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Manoj Mehrotra, Hiroaki Niimi: Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices. Texas Instruments Incorporated, Frederick J Telecky Jr, W James Brady III, April 3, 2007: US07199020 (5 worldwide citation)

A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combine ...


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Puneet Kohli, Manoj Mehrotra, Shaoping Tang: High threshold NMOS source-drain formation with As, P and C to reduce damage. Texas Instruments Incorporated, Jacqueline J Garner, Wade J Brady III, Frederick J Telecky Jr, June 15, 2010: US07736983 (5 worldwide citation)

Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly used to reduce phosphorus diffusion ...