1
Xavier Baie
Doris Bruce B, Chidambarrao Dureseti, Baie Xavier, Mandelman Jack A, Sadana Devendra K, Schepis Dominic J: (fet) Having stress channel and its manufacturing method. Internatl Business Mach Corp &Lt IBM&Gt, July 8, 2004: JP2004-193596 (2 worldwide citation)

PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while t ...


2
Xavier Baie
Chidambarrao Dureseti, Dokumaci Omer H, Doris Bruce B, Mandelman Jack A, Baie Xavier: Stress inducing spacers. International Business Machines Corporation, April 1, 2005: TWI230463 (1 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region within the spacers are formed adjacent both ...


3
Xavier Baie
Chidambarrao Dureseti, Dokumaci Omer H, Doris Bruce B, Mandelman Jack A, Baie Xavier: Stress inducing spacers. Ibm, li zheng liu wei, November 22, 2006: CN200610082638

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


4
Xavier Baie
Doris Bruce B, Chidambarrao Dureseti, Baie Xavier, Mandelman Jack A, Sandana Devendra K, Schepis Dominic J: Field effect transistor with improved charge carrier mobility and manufacturing method thereof. International Business Machines Corporation, June 18, 2004: KR1020030086391

PURPOSE: An FET(Field Effect Transistor) and a manufacturing method thereof are provided to improve charge carrier mobility by using a compressive film. CONSTITUTION: An FET includes a channel area(22), an undercut area under the channel area, a gate electrode(28) on the channel area, and a compress ...


5

6
Xavier Baie
Doris Bruce B, Chidambarrao Dureseti, Baie Xavier, Mandelman Jack A, Sadana Devendra K: Field effect transistor with stressed channel and method for making same. International Business Machines Corporation, December 21, 2005: TWI246180

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


7

8
Divakaruni Rama, Gambino Jeffrey P, Mandelman Jack A, Rengarajan Rajesh: Structure and process integration for producing transistors having independently adjustable parameters. International Business Machines Corporation, Infineon Technologies Aktiengesellschaft, January 1, 2003: TW516232 (40 worldwide citation)

The process rules for manufacturing semiconductor devices such as MOSFET^s are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly re ...


9
Lewis L Suu, Gluschenkov Oleg, Mandelman Jack A, Radens Carl J: Vertical mosfet sram cell. Internatl Business Mach Corp &Lt IBM&Gt, July 8, 2004: JP2004-193588 (27 worldwide citation)

PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate.SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a ...


10
Adkisson James A, Divakaruni Ramachandra, Gambino Jeffrey P, Mandelman Jack A: Vertical transistor trench capacitor dram with soi logic devices. Ibm, April 24, 2002: EP1199745-A2 (16 worldwide citation)

A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped gla ...



Click the thumbnails below to visualize the patent trend.