1
Mahesh Mehendale, Shivaling Mahant Shetti, Manisha Agarwala, Mark G Harward, Robert J Landers: Field programmable gate array logic module configurable as combinational or sequential circuits. Texas Instruments Incorporated, Gerald E Laws, C Alan McClure, Richard L Donaldson, May 12, 1998: US05751162 (9 worldwide citation)

A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic modu ...


2
Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman: Circuits and methods for performance optimization of SRAM memory. TEXAS INSTRUMENTS INCORPORATED, Michael A Davis Jr, Charles A Brill, Frank D Cimino, August 15, 2017: US09734896

In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal ...


3
Per Torstein Roine, Vinod Menezes, Mahesh Mehendale, Vamsi Gullapalli, Premkumar Seetharaman: Circuits and methods for performance optimization of SRAM memory. TEXAS INSTRUMENTS INCORPORATED, Michael A Davis Jr, Frank D Cimino, July 5, 2016: US09384826

In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the c ...


4
Vijay KG Sindagi, Mahesh Mehendale: Early predicate evaluation to reduce power in very long instruction word processors employing predicate execution. Texas Instruments Incorporated, October 14, 2004: US20040205326-A1

This invention reduces redundant power consumption by early detection of predicate register values. This detects pending writes to the predicate registers. When there are no pending predicate register updates, the predicate value is read in the decode stage and a decision whether to nullify the inst ...


5
Alexander Tessarolo, Mahesh Mehendale: Apparatus and method for manipulating data for aligning the stack memory. Texas Instruments Incorporated, W Daniel Swayze Jr, W James Brady, Frederick J Telecky Jr, January 22, 2002: US06341344

A method and apparatus for manipulating data from a processor on a stack memory is disclosed. The method and apparatus comprises aligning a stack pointer (