Luigi Capodieci: Modification of mask layout data to improve writeability of OPC. Advanced Micro Devices, Amin Eschweiler & Turocy, March 28, 2000: US06044007 (207 worldwide citation)

A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner ...


Luigi Capodieci, Juan Andres Torres Robles, Lodewijk Hubertus Van Os: Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques. ASML Masktools, ASM Lithography, McDermott Will & Emery, April 22, 2003: US06553562 (171 worldwide citation)

A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying “horizontal” critical features and “vertical” critical features from a plurality of features forming a layout; identifying interconnection areas which ...


Luigi Capodieci: Microdevice fabrication method using regular arrays of lines and spaces. Advanced Micro Devices, Renner Otto Boisselle & Sklar, June 24, 2003: US06583041 (57 worldwide citation)

A method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate la ...

Cyrus Tabery, Chris Haidinyak, Todd P Lukanc, Luigi Capodieci, Carl P Babcock, Hung eil Kim, Christopher A Spence: Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results. Advanced Micro Devices, Renner Otto Boisselle and Sklar, April 17, 2007: US07207017 (51 worldwide citation)

A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clip ...

Luigi Capodieci: Optical proximity correction (OPC) technique using generalized figure of merit for photolithograhic processing. Advanced Micro Devices, Renner Otto Boisselle & Sklar, December 20, 2005: US06978438 (34 worldwide citation)

A method and associated computer program for making optical proximity corrections for a reticle layout topology. Edge segments of the reticle layout topology are manipulated to generate a corrected reticle layout accounting for optical distortions and, based on the corrected reticle layout, a plural ...

Anna Minvielle, Luigi Capodieci, Christopher Spence: Utilizing electrical performance data to predict CD variations across stepper field. Advanced Micro Devices, Renner Otto Boisselle & Sklar, May 13, 2003: US06562639 (33 worldwide citation)

In order to determine an amount of critical dimension variation to expect across a surface of a final production wafer, a plurality of test structures are formed on a test wafer. The test structures are preferably of a type commonly found on the final production wafer and may for example, include tr ...

Carl Babcock, Luigi Capodieci: Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing. Advanced Micro Devices, Renner Otto Boisselle & Sklar, July 18, 2006: US07080349 (25 worldwide citation)

A method for developing an optimized layout fragmentation script for an optical proximity correction (OPC) simulation tool. A test pattern layout having at least one structure representing a portion of the integrated circuit layout is provided. Optical proximity correction is iteratively conducted o ...

Todd P Lukanc, Cyrus E Tabery, Luigi Capodieci, Carl Babcock, Hung eil Kim, Christopher A Spence, Chris Haidinyak: System and method for design rule creation and selection. Advanced Micro Devices, Winstead Sechrest & Minick P C, March 20, 2007: US07194725 (20 worldwide citation)

A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules c ...

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