1
Rino Micheloni, Luca Crippa, Alessia Marelli: Error correction code technique for improving read stress endurance. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 8, 2014: US08694855 (27 worldwide citation)

A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and gener ...


2
Rino Micheloni, Luca Crippa, Roberto Ravasio: Double page programming system and method. STMicroelectronics S r l, Graybeal Jackson Haley, April 29, 2008: US07366014 (26 worldwide citation)

A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into ...


3
Luca Crippa, Chiara Missiroli, Roberto Ravasio, Rino Micheloni, Angelo Bovino: Page buffer circuit and method for multi-level NAND programmable memories. STMicroelectronics S r l, Graybeal Jackson Haley, February 26, 2008: US07336538 (15 worldwide citation)

A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second mem ...


4
Rino Micheloni, Luca Crippa: Bandgap voltage reference circuit. STMicroelectronics S r l, James H Morris, Wolf Greenfield & Sacks P C, November 4, 2003: US06642776 (13 worldwide citation)

Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circui ...


5
Giancarlo Ragone, Miriam Sangalli, Luca Crippa, Rino Micheloni: Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile flash memories. Schwabe Williamson & Wyatt, May 12, 2009: US07532061 (10 worldwide citation)

Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an en ...


6
Luca Crippa, Rino Micheloni: Sensing circuit for a semiconductor memory. STMicroelectronics S r l, Lisa K Jorgenson, Stephen Bongini, Fleit Kain Gibbons Gutman Bongini & Bianco P L, February 27, 2007: US07184348 (9 worldwide citation)

A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one comparator. The first ...


7
Luca Crippa, Rino Micheloni: Circuit and method for electrically programming a non-volatile semiconductor memory via an additional programming pulse after verification. Blakely Sokoloff Taylor & Zafman, March 3, 2009: US07499332 (8 worldwide citation)

A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; and repeating the acts of applying and verifying until the reaching of a target programming sta ...


8
Rino Micheloni, Giovanni Campardo, Luca Crippa: Read circuit for a nonvolatile memory. STMicroelectronics S r l, Lisa K Jorgenson, Robert Iannucci, Seed IP Law Group PLLC, December 4, 2001: US06327184 (6 worldwide citation)

The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of th ...


9
Rino Micheloni, Luca Crippa: Circuit and method for timing multi-level non-volatile memories. STMicroelectronics S r l, Lisa K Jorgenson, Dennis M de Guzman, Seed IP Law Group PLLC, June 3, 2003: US06574146 (6 worldwide citation)

A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply ...


10
Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Rino Micheloni: Circuit and method for retrieving data stored in semiconductor memory cells. Blakely Sokoloff Taylor & Zafman, January 6, 2009: US07474577 (4 worldwide citation)

A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one ...