1
Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system. Sun Microsystems, Steven F Caserza, Flehr Hohbach Test Albritton & Herbert, May 18, 1999: US05905998 (81 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


2
Satyanarayana Nishtala, Zahir Ebrahim, William C Van Loo, Kevin Normoyle, Leslie Kohn, Louis F Coffin III: Packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, May 27, 1997: US05634068 (77 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems inclu ...


3
Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, August 5, 1997: US05655100 (76 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


4
Charles E Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin B Normoyle, Louis F Coffin III, Leslie Kohn: Method and apparatus for reducing power consumption in a computer network without sacrificing performance. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, November 25, 1997: US05692197 (69 worldwide citation)

A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independentl ...


5
Satyanarayana Nishtala, Zahir Ebrahim, William C Van Loo, Paul Loewenstein, Sue K Lee, Louis F Coffin III: Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system. Sun Microsystems, Test Albritton & Herbert Flehr Hohbach, December 3, 1996: US05581729 (67 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


6
William C Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie Kohn, Louis F Coffin III, Charles E Narad: Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, August 12, 1997: US05657472 (56 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


7
Dan Q Tu, Louis F Coffin III: Simultaneous tuning of multiple channels using intermediate frequency sub-sampling. Microsoft Corporation, Workman Nydegger, May 3, 2005: US06888888 (53 worldwide citation)

Methods and systems for processing a single sub-channel that includes two or more combined channels. Using intermediate frequency sub-sampling, two or more channels from a broad band signal are combined into a single sub-channel for further analog and digital processing. Each of the two or more chan ...


8
Louis F Coffin III: Satellite receiving system with transmodulating outdoor unit. Microsoft Corporation, Lee & Hayes PLLC, March 7, 2006: US07010265 (41 worldwide citation)

A home satellite receiving system employs a transmodulating outdoor unit (ODU) that tunes to multiple signals, demodulates those signals into streams of data packets, and filters the streams of data packets to select data packets pertaining to viewer-specified programs. The ODU then constructs an in ...


9
William C Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, November 4, 1997: US05684977 (39 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


10
Louis F Coffin III: Method and apparatus for adjusting signal component strength. Microsoft Corporation, Lee & Hayes PLLC, July 4, 2006: US07072627 (35 worldwide citation)

A first signal component is received having a first signal strength and a second signal component is received having a second signal strength. A difference is identified between the first signal strength and the second signal strength. A determination is made as to whether the difference between the ...