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LOPATIN SERGEY D: Composite materials containing metallized carbon nanotubes and nanofibers. Applied Materials, Patterson B Todd, October 21, 2010: WO/2010/120813 (4 worldwide citation)

A method and apparatus are provided for the cost effective formation of a composite material which includes metallized carbon nanotubes and/or nanofibers that can be used to form portions of an energy storage device, such as a lithium ion battery. In one embodiment, carbon nanotubes are formed on a ...


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BACHRACH Robert Z, WANG Connie P, LOPATIN Sergey D, BOLANDI Hooman, BABAYANTS Ruben, BROWN Karl M, KUTNEY Michael C, OLGADO Donald J K: MODULE DE DÉPÔT PAR PULVÉRISATION POUR UN SYSTÈME DE TRAITEMENT EN LIGNE, SPRAY DEPOSITION MODULE FOR AN IN-LINE PROCESSING SYSTEM. Applied Materials, BACHRACH Robert Z, WANG Connie P, LOPATIN Sergey D, BOLANDI Hooman, BABAYANTS Ruben, BROWN Karl M, KUTNEY Michael C, OLGADO Donald J K, PATTERSON B Todd, March 22, 2012: WO/2012/036908 (2 worldwide citation)

In one embodiment, an apparatus for simultaneously depositing an anodically or cathodically active material on opposing sides of a flexible conductive substrate is provided. The apparatus comprises a chamber body defining one or more processing regions in which a flexible conductive substrate is exp ...


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Tripsas Nicholas, Buynoski Matthew S, Pangrle Suzette, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, April 19, 2006: GB2419231-A

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


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Lyons Christopher F, Chang Mark S, Lopatin Sergey D, Subramanian Ramkumar, Cheung Patrick, Ngo Minh Van, Oglesby Jane V: Sidewall formation for high density polymer memory element array. Advanced Micro Devices, September 6, 2006: EP1697992-A2

Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cell ...


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Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V, sCOLLOPY Daniel R, February 3, 2005: WO/2005/010892

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


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Lyons Christopher F, Chang Mark S, Lopatin Sergey D, Subramanian Ramkumar, Cheung Patrick, Ngo Minh Van, Oglesby Jane V: Sidewall formation for high density polymer memory element array. Advanced Micro Devices, Lyons Christopher F, Chang Mark S, Lopatin Sergey D, Subramanian Ramkumar, Cheung Patrick, Ngo Minh Van, Oglesby Jane V, sDRAKE Paul S, May 19, 2005: WO/2005/045935

Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cell ...


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Lopatin Sergey D, Ngo Minh Van, Tran Minh Quoc: Amorphized barrier layer for integrated circuit interconnects. Advanced Micro Devices, sRODDY Richard J, May 23, 2002: WO/2002/041391

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate [200] with a semiconductor device. A dielectric layer [208] is on the semiconductor substrate [200] and has an opening provided therein. An amorphized barrier layer [226] lines the opening and a seed ...



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