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Zhao Yongqing, Liu Anhong, Huang Xiangming, Li Yizhang, Li Yaorong: Image sensor module package structure. Chipmos Technologies, shouning zhanghua hui, April 25, 2007: CN200510114333

The invention relates to an image sensor mould package structure. Wherein, dual connecting pads are on the first surface of said glass base plate and outside the incident area of base plate; one wire layer is on the second surface of said glass base plate to be electrically connected to the connecti ...


2
Liu Anhong, Wang Yonghe, Zhao Yongqing, Li Yaorong: Crystal wafer testing method and structure of led. Nanmao Science &Amp Technology, shouning zhanghua hui, May 2, 2007: CN200510114523

A method for testing grade of chip on LED includes sticking an adhesive tape at back said chip, cutting it to be multiple LED chip with adhesive tape, contacting P type and N type of electrodes on those chips by detection card with multiple detection structures in ohm mode, setting a light detector ...


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Huang Xiangming, Liu Anhong, Li Yizhang, Lin Yongzhi, He Shujing: Connection method for chip and bearer. Chipmos Technologies, chenliang, August 13, 2008: CN200710001892

The invention disclsoes joint method of a chip and a bearing device. A wafer is provided, which has a plurality of connecting pad and a plurality lugs arranged on the connecting pad. An adhesive layer with two stage characteristics is form on the wafter to coat the lug. The adhesive layer with two s ...


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Huang Xiangming, Zhao Yongqing, Li Yizhang, Liu Anhong: Packaging structure of bug-hole downwards wafer and manufacturing method thereof. ChipMOS Technologies, Shou Ning, Zhang Huahui, September 30, 2009: CN200910137256

The present invention relates to a packaging structure of bug-hole downwards wafer and a manufacturing method thereof. According to the manufacturing method of packaging structure of bug-hole downwards wafer, firstly the provided wafer carrier comprises a flat surface and a plurality of bug holes, w ...


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Liu Anhong, He Shujing, Huang Xiangming, Li Yizhang, Cai Haoyin: Packaging structure with substrate post and packaging method thereof. ChipMOS Technologies Bermuda ChipMOS Technologies, Ren Yongwu, February 24, 2010: CN200810213647

The invention discloses a packaging structure, which comprises a substrate, a patterned pad mask layer, a plurality of conducting posts, a plurality of solder balls, a chip and a patterned second under bump metal layer, wherein the substrate is provided with a front and a back, and the front is prov ...


7
Huang Xiangming, Liu Anhong, Li Yizhang, Cai Haoyin, He Shujing: Conductive structure of chip. ChipMOS Technologies, Lu Jia, October 21, 2009: CN200810092277

The invention relates to a conductive structure of a chip, which comprises a grounding layer, a dielectric layer, a redistributing layer, a convex-block lower metal layer and a welding block, wherein the grounding layer is connected with a grounding bonding pad of the chip, and the dielectric layer ...


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Huang Xiangming, Liu Anhong, Li Yizhang, Cai Haoyin, He Shujing: Conductive structure of chip and manufacture method thereof. ChipMOS Technologies, Lu Jia, November 4, 2009: CN200810095280

The invention relates to a conductive structure of a chip and a manufacture method thereof. After a redistributed layer is formed, an electroanalysis-free plating technology is used for forming a lower metal layer of a convex block, and a welding block is formed on the lower metal layer of the conve ...


9
Huang Xiangming, Liu Anhong, Li Yizhang, Cai Haoyin, He Shujing: Package structure for stacked type integrated circuit chip. ChipMOS Technologies, Chen Liang, November 11, 2009: CN200810099204

The invention provides a package structure for a stacked type integrated circuit chip, comprising integrated circuit chips, a first medium layer, a circuit board and a second pattern conducting layer. The circuit board covers the integrated circuit chips and partially covers the first medium layer a ...


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Wang Davidwei, Liu Anhong, Tsai Haoyin, Huang Hsiangming, Lee Yichang, Ho Shuching: Package structure and method for forming and manufacturing thereof, chip piling structure. Nanmao Sci & Tech, Ren Yongwu, January 13, 2010: CN200910003189

The present invention provides a package structure and a method for forming and manufacturing thereof, a chip piling structure. The package structure comprises a first chip piling structure, a plurality of silicon passage components are arranged on the chip as a route for electrical connecting, whic ...