1
Lishing Liu: Translation of multiple virtual pages upon a TLB miss. International Business Machines Corporation, Peter L Michaelson, Raymond R Moser Jr, January 25, 1994: US05282274 (84 worldwide citation)

Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and specifically for increasing the speed of such translations by translating multiple contiguous virtual page addre ...


2
Patrick M Gannon, Michael Ignatowski, Matthew A Krygowski, Lishing Liu, Donald W Price, William K Rodiger, Gregory Salyer, Yee Ming Ting, Michael P Witt: Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data. International Business Machines Corporation, Bernard M Goldman, November 23, 1993: US05265232 (79 worldwide citation)

A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, ...


3
Lishing Liu: Cache coherence mechanism based on locking. International Business Machines Corporation, Jack M Arnold, Terry J Ilardi, October 4, 1988: US04775955 (74 worldwide citation)

A method and apparatus is provided for associating in cache directories the Control Domain Identifications (CDIDs) of software covered by each cache line. Through the use of such provision and/or the addition of Identifications of users actively using lines, cache coherence of certain data is contro ...


4
Lishing Liu: Sequential prefetching with deconfirmation. International Business Machines Corporation, Ronald L Drumheller, December 25, 1990: US04980823 (70 worldwide citation)

A computer memory management method for cache memory uses a deconfirmation technique to provide a simple sequential prefetching algorithm. Access sequentially is predicted based on simple histories. Each memory line in cache memory is associated with a bit in an S-vector, which is called the S-bit f ...


5
Lishing Liu: History table for set prediction for accessing a set associative cache. International Business Machines Corporation, Ronald L Drumheller, May 23, 1995: US05418922 (56 worldwide citation)

A cache control maintains a history table SETLAT for the prediction of line entry (i.e., set member) within a congruence class for cache accessing. For a given cache access, a SETLAT entry can be selected based on the requesting logical address bits directly. The selection of a SETLAT entry may also ...


6
Russell D Hoover, John C Willis, Donald F Baldus, Frederick J Ziegler, Lishing Liu: System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system. International Business Machines Corporation, Owen Gamon, Andrew J Dillon, February 18, 1997: US05604882 (54 worldwide citation)

A multiprocessor in which processing units have local private caches and records are stored on at least a first global storage control unit. An interconnection system provides node to node data and synchronization communications between processing units and the first global storage control unit. The ...


7
Joseph O Celtruda, Kein A Hua, Anderson H Hunt, Lishing Liu, Jih Kwon Peir, David R Pruett, Joseph L Temple III: Translation look ahead based cache access. International Business Machines Corporation, John D Flynn, Blaney Harper, Maurice H Klitzman, September 15, 1992: US05148538 (53 worldwide citation)

This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the real address used in the cache memory will b ...


8
Lishing Liu: Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line. International Business Machines Corporation, Ronald L Drumheller, Richard M Ludwin, May 31, 1994: US05317716 (48 worldwide citation)

A method for increasing cache concurrency in a multiprocessor system. In a multiprocessor system having a plurality of processors each having a local cache in order to increase concurrency the directory entry for a line in local cache will be assigned an LCH bit for locally changed status. If the la ...


9
Lishing Liu: Access authorization table for multi-processor caches. International Business Machines Corporation, Whitham & Marhoefer, July 20, 1993: US05230070 (38 worldwide citation)

A multi-processor (MP) system having shared storage is provided with locking of exclusivity status and read only status in multi-processor caches. The multi-processor system includes a plurality of processors, a shared main storage and a storage control element (SCE). The storage control element inc ...


10
Lishing Liu: History based branch prediction accessed via a history based earlier instruction address. International Business Machines Corporation, Ronald L Drumheller, April 9, 1996: US05507028 (38 worldwide citation)

An improved history table is disclosed in which at least some of the entries are stored and accessed based upon the address of an instruction which historically preceeds the branch instruction itself. The access address may be used to determine the location of the entry in the table and/or may be st ...