1
Ahearn Thomas P, Capowski Robert S, Christensen Neal T, Gannon Patrick M, Lee Arlin E, Liptay John S: Virtual memory system. International Business Machines Corporation, December 25, 1973: US3781808 (63 worldwide citation)

This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses o ...


2
Gannon Patrick M, Liptay John S, Rymarczyk James W: Data processing apparatus. Ibm, November 16, 1979: FR2423822-A1

Improved processor performance when dealing with variable field length operands is achieved by incorporating a fetching mechanism A9 which can operate in an overlapped mode with the instruction execution unit EF. Further improvement is provided by aligning operands within the fetching mechanism A13 ...


3
Liptay John S: Data processing system. Ibm, October 12, 1979: FR2420168-A1

In a data processing system which predecodes and queues a plurality of instructions for sequential presentation to an execution unit, and which includes a plurality of instruction-addressable general registers (56) which can be utilized for temporary data storage or source of address modifying infor ...


4
HUGHES JEFFREY F, LIPTAY JOHN S, RYMARCZYK JAMES W, STONE STANLEY E: [fr] DISPOSITIF DE MISE EN SEQUENCE DINSTRUCTIONS. IBM, July 27, 1979: FR2413716-A1

[fr] DISPOSITIF POUR EXTRAIRE PAR ANTICIPATION DE LA MEMOIRE ET PRE-DECODER PLUSIEURS SEQUENCES D'INSTRUCTIONS.


5
Hughes Jeffrey F, Stone Stanley E, Rymarczyk James W, Liptay John S: Mecanisme de traitement de branchements a chaines multi-instructions, Multi-instruction stream branch processing mechanism. Interntional Business Machines Corporation, GAMMIE ALEXANDER P, June 16, 1981: CA1103369

MULTI-INSTRUCTION STREAM BRANCH PROCESSING MECHANISM ABSTRACT In a high-performance computer which prefetchesand predecodes instructions for sequential presentationto an execution unit, at least three separately gatedand sequenced instruction buffers for prefetchedinstructions permit continued seque ...


6
Liptay John S: Systeme de gestion des registres dun processeur dordinateur a execution declassee des instructions, Register management system in a computer processor with out-of-sequence instruction execution. International Business Machines Corporation, SAUNDERS RAYMOND H, June 9, 1992: CA1303225

Abstract Of The Disclosure A register management system has more physicalregisters for general purpose use than are named in thearchitectural system. A renaming system identifiesparticular physical registers to perform as architectedaddressable or general purpose registers. An arraycontrol list (ACL ...


7

8
Comfort Steven T, Liptay John S, Webb Charles F: Data processor. Internatl Business Mach Corp &Lt IBM&Gt, November 16, 1993: JP1993-303492

PURPOSE: To provide a system and method by which CPUs can continue operations beyond a serializing point before the architecture specifies when the operations are permitted. CONSTITUTION: Whether or not proper processed results are obtained after serialization is confirmed. When the certainty of the ...


9
Berstick Viktors, Liptay John S, Pedersen Raymond James: Computer system. Internatl Business Mach Corp &Lt IBM&Gt, September 28, 1993: JP1993-250157

PURPOSE: To accelerate the processing speed of an RX instruction without any limit factor such as the link of memory/load. CONSTITUTION: Concerning a computer system having a system memory, (m) pieces of logical register for architecture design and the array of (n) pieces of physical registers (n>m) ...


10
Bruce C Jamey, Mark A Check, Liptay John S: Method of detecting address generating interlock and its system. Internatl Business Mach Corp &Lt IBM&Gt, May 10, 2002: JP2002-132500

PROBLEM TO BE SOLVED: To provide a method of detecting an address generating interlock and its system in a pipeline data processor.SOLUTION: A step accumulating a plurality of vectors over predefined numbers of a processor clock cycle and following vectors are responded to following clock cycles in ...