1
Reza A Pagaila, Byung Tai Do, Linda Pei Ee Chua: Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die. STATS ChipPAC, Robert D Atkins, Patent Law Group Atkins & Associates P C, January 17, 2012: US08097490 (48 worldwide citation)

A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the e ...


2
Reza A Pagaila, Linda Pei Ee Chua, Byung Tai Do: Semiconductor device and method of forming through vias with reflowed conductive material. STATS ChipPAC, Robert D Atkins, June 22, 2010: US07741156 (47 worldwide citation)

A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining i ...


3
Heap Hoe Kuan, Seng Guan Chow, Linda Pei Ee Chua: Method of making a wafer level integration package. STATS ChipPAC, Robert D Atkins, June 30, 2009: US07553752 (45 worldwide citation)

A semiconductor package is made by providing a wafer having a first electrical contact pad integrated into a top surface of the wafer, forming a through-hole interconnection extending downward from a first surface of the first electrical contact pad, electrically connecting a die to a second surface ...


4
Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua: Semiconductor package having through-hole via on saw streets formed with partial saw. STATS ChipPAC, Robert D Atkins, September 8, 2009: US07585750 (30 worldwide citation)

A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not co ...


5
Linda Pei Ee Chua, Byung Tai Do, Reza A Pagaila: Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant. STATS ChipPAC, Robert D Atkins, Patent Law Group Atkins & Associates P C, October 15, 2013: US08558392 (24 worldwide citation)

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface ...


6
Reza A Pagaila, Byung Tai Do, Linda Pei Ee Chua: Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die. STATS ChipPAC, Robert D Atkins, Patent Law Group Atkins & Associates P C, October 9, 2012: US08283205 (21 worldwide citation)

A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the e ...


7
Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua: Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer. STATS ChipPAC, Robert D Atkins, November 9, 2010: US07829998 (20 worldwide citation)

A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or fu ...


8
Seng Guan Chow, Linda Pei Ee Chua, Heap Hoe Kuan: Integrated circuit package system with penetrable film adhesive. Stats Chippac, Ishimaru & Associates, Mikio Ishimaru, Stanley M Chang, September 4, 2012: US08258015 (19 worldwide citation)

An integrated circuit package system including: providing a wire bonded die with an active side and a bond wire connected thereto; forming a penetrable film adhesive on the active side and partially encapsulating the bond wire; mounting an interposer, having a first functional side facing up away fr ...


9
Byung Tai Do, Heap Hoe Kuan, Reza A Pagaila, Linda Pei Ee Chua: Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device. STATS ChipPAC, Robert D Atkins, February 9, 2010: US07659145 (18 worldwide citation)

A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The c ...


10
Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua: Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer. STATS ChipPAC, Robert D Atkins, Patent Law Group Atkins & Associates P C, August 21, 2012: US08247268 (15 worldwide citation)

A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or fu ...