1
Leslie D Kohn, Kunle A Olukotun, Michael K Wong: DRAM power management. Sun Microsystems, Martine Penilla & Gencarella, August 30, 2005: US06938119 (137 worldwide citation)

A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. ...


2
Leslie D Kohn: Pipelined apparatus and method for controlled loading of floating point data in a microprocessor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 13, 1992: US05155816 (128 worldwide citation)

A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data ...


3
Leslie D Kohn: Method and apparatus for graphics display data manipulation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 14, 1992: US05081698 (115 worldwide citation)

Special purpose graphics instructions are provided to facilitate hidden surface elimination. A Z-buffer check instruction performs multiple, simultaneous unsigned-integer (ordinal) comparisons of newly computed distance (Z) values with the contents of a Z-buffer. Distances of points to be drawn are ...


4
Leslie D Kohn: Method for parallel instruction execution in a computer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 31, 1993: US05241636 (100 worldwide citation)

A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one more single instruction is executed before dual- ...


5
Leslie D Kohn: Method and apparatus for graphics data interpolation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 20, 1992: US05157388 (54 worldwide citation)

Special purpose graphics instructions are provided to implement linear interpolation of pixel attributes such as a distance (Z) value or color intensity. Multiple fixed-point real number additions are performed in parallel in a 64-bit adder. The real number sums are truncated upon being loaded in a ...


6
Leslie D Kohn, Kunle A Olukotun, Michael K Wong: Multi-core multi-thread processor. Sun Microsystems, Martine Penilla & Gencarella, April 24, 2007: US07209996 (43 worldwide citation)

In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plu ...


7
Leslie D Kohn, Michael K Wong: Method and apparatus for a packet classifier. Sun Microsystems, Martine Penilla & Gencarella, July 24, 2007: US07248585 (39 worldwide citation)

In one embodiment, a method for efficiently classifying packets for a multi-processor/mutli-thread environment is provided. The method initiates with receiving a packet. Then, header information is extracted form the received packet. Next, a first hash value is calculated. Then, a field of interest ...


8
Leslie D Kohn, Shai Rotem: Parallel protection checking in an address translation look-aside buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 23, 1993: US05265227 (36 worldwide citation)

A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual addr ...


9
Diego P de Garrido, Kamil Metin Uz, Leslie D Kohn, Didier LeGall: Motion compensated de-interlacing. LSI Logic Corporation, Christopher P Maiorana PC, January 28, 2003: US06512550 (28 worldwide citation)

A method of motion compensation using temporal support of multiple fields of video to produce a progressive frame. The moving average of the motion compensated field lines temporally adjacent to the field to be de-interlaced are used, after a non-linear filtering, as the missing lines to complete th ...


10
Diego P de Garrido, Kamil Metin Uz, Leslie D Kohn, Didier LeGall: Motion compensated de-interlacing. LSI Logic Corporation, December 18, 2001: US06331874 (27 worldwide citation)

An algorithm based on motion compensation uses a temporal support of five fields of video to produce a progressive frame. The moving average of the motion compensated field lines temporally adjacent to the field to be de-interlaced are used, after a non-linear filtering, as the missing lines to comp ...