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David D Andaleon, Leonard M Napolitano Jr, G Robert Redinbo, William O Shreeve: Fault-tolerant corrector/detector chip for high-speed data processing. The United States of America represented by the United States Department of Energy, Karuna Ojanen, James H Chafin, William R Moser, March 1, 1994: US05291496 (79 worldwide citation)

An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided wi ...


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Leonard M Napolitano Jr: Lambda network having 2.sup.m-1 nodes in each of m stages with each node coupled to four other nodes for bidirectional routing of data packets between nodes. November 28, 1995: US05471623 (34 worldwide citation)

The Lambda network is a single stage, packet-switched interprocessor communication network for a distributed memory, parallel processor computer. Its design arises from the desired network characteristics of minimizing mean and maximum packet transfer time, local routing, expandability, deadlock avo ...