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Wendell P Noble, Leonard Forbes, Kie Y Ahn: Memory cell having a vertical transistor with buried source/drain and dual gates. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, November 21, 2000: US06150687 (255 worldwide citation)

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of th ...


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Kie Y Ahn, Leonard Forbes, Eugene H Cloud: Structure and method for a high-performance electronic packaging assembly. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, May 27, 2003: US06570248 (228 worldwide citation)

An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can c ...


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Kie Y Ahn, Leonard Forbes: Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, July 26, 2005: US06921702 (209 worldwide citation)

A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor fo ...


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Wendell P Noble, Leonard Forbes, Kie Y Ahn: Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines. Micro Technology, Schwegman Lundberg Woessner & Kluth P A, June 6, 2000: US06072209 (205 worldwide citation)

A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transi ...


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Leonard Forbes, Joseph E Geusic: Alternate method and structure for improved floating gate tunneling devices. Micron Technology, Schwegman Woessner & Kluth P A Lundberg, February 15, 2000: US06025627 (202 worldwide citation)

A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using "self-structured masks" and a controlled etch to form nanometer scale microtip arrays to form the textured su ...


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Leonard Forbes, Wendell P Noble: High density flash memory. Micron Technology, Schwegman Lundberg Woessner & Lundberg P A, August 10, 1999: US05936274 (198 worldwide citation)

A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control ga ...


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Leonard Forbes, Wendell P Noble: High density flash memory. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, November 7, 2000: US06143636 (197 worldwide citation)

A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control ga ...


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Leonard Forbes, Wendell P Noble, Kie Y Ahn: Method of making memory cell with vertical transistor and buried word and body lines. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, June 1, 1999: US05909618 (189 worldwide citation)

An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provi ...


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Leonard Forbes, Wendell P Noble: Programmable memory address decode array with vertical transistors. Micron Technology, Schwegan Lundberg Woessner & Kluth P A, November 23, 1999: US05991225 (188 worldwide citation)

A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction b ...



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