1
David J Corisis, Tracy Reynolds, Michael Slaughter, Daniel Cram, Leland R Nevill, Jerrold L King: Integrated circuit package including lead frame with electrically isolated alignment feature. Micron Technology, TraskBritt, June 12, 2001: US06246108 (146 worldwide citation)

An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature inc ...


2
David J Corisis, Tracy Reynolds, Michael Slaughter, Daniel Cram, Leland R Nevill, Jerrold L King: Integrated circuit package alignment feature. Micron Technology, Trask Britt & Rossa, April 11, 2000: US06048744 (125 worldwide citation)

An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature inc ...


3
Jerrold L King, Leland R Nevill: Semiconductor chip package. Micron Technology, Workman Nydegger & Seeley, March 6, 2001: US06198172 (95 worldwide citation)

An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substa ...


4
Ray J Beffa, William K Waller, Eugene H Cloud, Warren M Farnworth, Leland R Nevill: Self-test of a memory device. Micron Technology, Dickstein Shapiro Morin & Oshinsky, June 8, 1999: US05910921 (46 worldwide citation)

DRAM self-test circuitry, when triggered by an external signal, performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. ...


5
Ray Beffa, Leland R Nevill, Warren M Farnworth, Eugene H Cloud, William K Waller: Wafer level burn-in of memory integrated circuits. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, May 15, 2001: US06233185 (40 worldwide citation)

A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit l ...


6
Stanley N Protigal, Web Foo Chern, Ward D Parkinson, Leland R Nevill, Gary M Johnson, Thomas M Trent, Kevin G Duesman: Memory module having on-chip surge capacitors. Micron Technology, April 26, 1994: US05307309 (40 worldwide citation)

A SIMM (single in-line memory module) board is provided with a plurality of semiconductor memory devices which include, as a part of each memory device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the memory device to the board. By connecting the on-c ...


7
Warren M Farnworth, Leland R Nevill, Raymond J Beffa, Eugene H Cloud: Reduced terminal testing system. Micron Technology, Trask Britt & Rossa, November 30, 1999: US05994915 (37 worldwide citation)

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a pre ...


8
Gary M Johnson, Leland R Nevill: Short-resistant decoupling capacitor system for semiconductor circuits. Micron Technology, Angus C Fox III, Stanley N Protigal, Jon Busack, November 7, 1989: US04879631 (37 worldwide citation)

A decoupling capacitor system for improving the reliability of digital logic circuit boards such as single inline memory modules which use surface-mount decoupling capacitors. The system comprises one or more units of two or more series-connected capacitors connected between the chip supply voltage ...


9
Warren M Farnworth, Leland R Nevill, Raymond J Beffa, Eugene H Cloud: Reduced terminal testing system. Micron Technology, TraskBritt PC, September 18, 2001: US06292009 (32 worldwide citation)

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a pre ...


10
Leland R Nevill, Ray Beffa, Warren M Farnworth, Gene Cloud: Self-test circuit for memory integrated circuits. Micron Technology, Seed and Berry, November 9, 1999: US05982682 (32 worldwide citation)

A sense amplifier senses and stores data from a memory cell in an array of memory cells arranged in rows and columns. The sense amplifier includes a sense circuit having a pair of first and second complementary digit lines which senses a voltage differential between the first and second complementar ...



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