1
Michael Putrino, Lee E Eisen: Load-store unit and method of loading and storing single-precision floating-point registers in a double-precision architecture. International Business Machines Corporation, Casimer K Salys, Brian F Russell, Andrew J Dillon, September 8, 1998: US05805475 (20 worldwide citation)

A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is ex ...


2
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell A Reininger: Method and system for recoding noneffective instructions within a data processing system. International Business Machines Corporation, Michael A Davis Jr, Andrew J Dillon, April 8, 1997: US05619408 (14 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...


3
Lee E Eisen, Robert T Golla, Christopher H Olson, Michael Putrino: Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization. International Business Machines Corporation, Michael A Davis, Brian F Russell, Andrew J Dillon, October 14, 1997: US05678016 (10 worldwide citation)

A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispa ...


4
Gregory W Alexander, Brian D Barrick, Lee E Eisen, John W Ward III: Dual-issuance of microprocessor instructions using dual dependency matrices. International Business Machines Corporation, Leveque IP Law PC, August 3, 2010: US07769984 (7 worldwide citation)

A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, th ...


5
Lee E Eisen, Belliappa M Kuttanna, Soummya Mallick, Rajesh B Patel: Method and system for efficiently fetching from cache during a cache fill operation. International Business Machines Corporation, Motorola, Casimer K Salys, Brian F Russell, Andrew J Dillon, April 27, 1999: US05897654 (7 worldwide citation)

A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions ...


6
Pradip Bose, Alper Buyuktosunoglu, Richard J Eickemeyer, Lee E Eisen, Philip G Emma, John B Griswell, Zhigang Hu, Hung Q Le, Douglas R Logan, Balaram Sinharoy: Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches. International Business Machines, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Brian P Verminski Esq, June 24, 2008: US07392366 (3 worldwide citation)

A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for a ...


7
Lee E Eisen, Robert T Golla, Soummya Mallick, Sung Ho Park, Rajesh B Patel, Michael Putrino: Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor. International Business Machines Corporation, Brian F Russell, Andrew J Dillon, September 15, 1998: US05809323 (2 worldwide citation)

A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the p ...


8
Gregory W Alexander, Lee E Eisen, Brian W Thompto, John W Ward III: Error detection enhancement in a microprocessor through the use of a second dependency matrix. International Business Machines Corporation, Casimer K Salys, McGinn IP Law Group PLLC, June 16, 2009: US07549095 (2 worldwide citation)

A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector inc ...


9
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell Adley Reininger: Method and system for recording noneffective instructions within a data processing system. International Business Machines Corporation, Motorola, Mark E McBurney, Brian F Russell, Andrew J Dillon, February 10, 1998: US05717587 (2 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...


10
Lee E Eisen, Lisa C Heller, Michael T Huffer, Eric M Schwarz: Instruction stream tracing of multi-threaded processors. International Business Machines Corporation, Steven F McDaniel, March 14, 2017: US09594561

A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of ...