1
Brian S Beaman, Fuad E Doany, Keith E Fogel, James L Hedrick Jr, Paul A Lauro, Maurice H Norcott, John J Ritsko, Leathen Shi, Da Yuan Shih, George F Walker: Three dimensional high performance interconnection package. International Business Machines Corporation, Daniel P Morris, December 6, 1994: US05371654 (318 worldwide citation)

The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is fo ...


2
Brain S Beaman, Fuad E Doany, Keith E Fogel, James L Hedrick Jr, Paul A Lauro, Maurice H Norcott, John J Ritsko, Leathen Shi, Da Yuan Shih, George F Walker: Method of forming a three dimensional high performance interconnection package. International Business Machines Corporation, Daniel P Morris, July 2, 1996: US05531022 (212 worldwide citation)

The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is fo ...


3
Hussein I Hanafi, Diane C Boyd, Kevin K Chan, Wesley Natzle, Leathen Shi: Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region. International Business Machines Corporation, Wan Yee Cheung, Scully Scott Murphy & Presser, December 9, 2003: US06660598 (82 worldwide citation)

A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an S ...


4
Panayotis Constantinou Andricacos, Madhav Datta, Hariklia Deligianni, Wilma Jean Horkans, Sung Kwon Kang, Keith Thomas Kwietniak, Gangadhara Swami Mathad, Sampath Purushothaman, Leathen Shi, Ho Ming Tong: Flip-Chip interconnections using lead-free solders. International Business Machines Corporation, Casey P August Esq, IBM Corporation, Ohlandt Greeley Ruggiero & Perle, May 1, 2001: US06224690 (76 worldwide citation)

An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhes ...


5
Guy Cohen, Michael A Guillorn, Alfred Grill, Leathen Shi: Accurate control of distance between suspended semiconductor nanowires and substrate surface. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, January 6, 2015: US08927968 (76 worldwide citation)

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride l ...


6
Kevin K Chan, Meikei Ieong, Alexander Reznicek, Devendra K Sadana, Leathen Shi, Min Yang: Strained silicon CMOS on hybrid crystal orientations. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Wan Yee Cheung et al, August 8, 2006: US07087965 (71 worldwide citation)

Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or ...


7
Samuel M Goldfarb, Paul R Herb, Joseph M Lukaitis, Leathen Shi: Non-destructive flex testing method and means. International Business Machines Corporation, Bernard M Goldman, June 13, 1995: US05424634 (60 worldwide citation)

Describes a process for applying non-destructive cyclical mechanical stress to planar items in order to simulate the effects of cyclical thermal stresses. Latent defects are accelerated and screened early in a manufacturing process.


8
Kathryn W Guarini, Meikei Ieong, Leathen Shi, Min Yang: Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes. International Business Machines Corporation, Wan Yee Cheung Esq, Scully Scott Murphy & Presser, December 14, 2004: US06830962 (59 worldwide citation)

The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top sem ...


9
Wu Song Huang, Igor Y Khandros, Ravi Saraf, Leathen Shi: Solder/polymer composite paste and method. International Business Machines Corporation, Perman & Green, November 5, 1991: US05062896 (51 worldwide citation)

An improved solder/polymer fluxless composite paste interconnection material having a low reflow temperature to form electrical contacts having good bonding strength and low contact resistance. The present pastes comprise a major proportion of a meltable metal alloy powder filler, free of noble meta ...


10
Kathryn W Guarini, Louis L Hsu, Leathen Shi, Dinkar V Singh, Li Kong Wang: Method of fabricating silicon devices on sapphire with wafer bonding at low temperature. International Business Machines Corporation, Scully Scott Murphy & Presser, Robert M Trepp Esq, June 28, 2005: US06911375 (31 worldwide citation)

Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling subst ...