1
Moataz A Mohamed, Heonchul Park, Le Trong Nguyen: Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor. Samsung Electronics, David T Millers, Skjerven Morrill MacPherson Franklin & Friel, November 2, 1999: US05978838 (197 worldwide citation)

An integrated multiprocessor architecture simplifies synchronization of multiple processing units. The multiple processing units constitute a general-purpose or control processor and a vector processor which has a single-instruction-multiple-data (SIMD) architecture so that multiple parallel process ...


2
Le Trong Nguyen: Single-instruction-multiple-data processing in a multimedia signal processor. David T Millers, Skjerven Morrill MacPherson Franklin & Friel, May 2, 2000: US06058465 (127 worldwide citation)

A vector processor architecture provides vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which manipulate operands associated with the vector registers. The data size defined by an instruction determin ...


3
Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang: System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox, August 1, 1995: US05438668 (121 worldwide citation)

A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the st ...


4
Le Trong Nguyen, Seungyoon Peter Song, Moataz A Mohamed, Heonchul Park, Roney Sau Don Wong: Single-instruction-multiple-data processing using multiple banks of vector registers. Samsung Electronics, David T Millers, Skjerven Morrill MacPherson Franklin & Friel, November 17, 1998: US05838984 (117 worldwide citation)

A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector reg ...


5
Le Trong Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te Li Lau, Sze Shun Wang, Quang H Trang: High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, September 24, 1996: US05560032 (112 worldwide citation)

A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. E ...


6
Derek J Lentz, Yasuaki Hagiwara, Te Li Lau, Cheng Long Tang, Le Trong Nguyen: Microprocessor architecture capable of supporting multiple heterogeneous processors. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, August 7, 2001: US06272579 (84 worldwide citation)

A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assi ...


7
Derek J Lentz, Yasuaki Hagiwara, Te Li Lau, Cheng Long Tang, Le Trong Nguyen: Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox, August 8, 1995: US05440752 (83 worldwide citation)

A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and ...


8
Le Trong Nguyen: Multiprocessor operation in a multimedia signal processor. Samsung Electronics, Skjerven Morrill, July 23, 2002: US06425054 (78 worldwide citation)

To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem prov ...


9
Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang: System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, April 8, 1997: US05619666 (74 worldwide citation)

A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the st ...


10
Le Trong Nguyen, Heonchul Park, Seong Rai Cho: Load and store unit for a vector processor. Samsung Electronics, David T Millers, Skjerven Morrill MacPherson Franklin & Friel, October 5, 1999: US05961628 (71 worldwide citation)

An apparatus coupled to a requesting unit and a memory. The apparatus includes a data path and a request control circuit. The data path is coupled to the requesting unit and the memory. The data path is for buffering a vector. The vector includes multiple data elements of a substantially similar dat ...