1
David B Papworth, Michael A Fetterman, Andrew F Glew, Lawrence O Smith III, Michael M Hancock, Beth Schultz: Apparatus and method for handling string operations in a pipelined processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 1995: US05404473 (78 worldwide citation)

In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a ...


2
Lawrence O Smith, S Dion Rodgers: Method and apparatus for processing events in a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 15, 2005: US06857064 (39 worldwide citation)

In a multithreaded processor, events are categorized according to which of a “soft” state clearing (“nuke”) process and a “hard” nuke process should be performed in response to each event. When an event is detected for a thread, either the soft nuke or hard nuke process is executed, according to the ...


3
Michael A Kozuch, James A Sutton II, David Grawrock, Gilbert Neiger, Richard A Uhlig, Bradley G Burgess, David I Poisner, Clifford D Hall, Andy Glew, Lawrence O Smith III, Robert George: Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 2006: US07024555 (30 worldwide citation)

An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection el ...


4
Gilbert Neiger, Steven M Bennett, Dion Rodgers, Richard A Uhlig, Lawrence O Smith III: Transitioning between virtual machine monitor domains in a virtual machine environment. Intel Corporation, Thomas R Lane, August 25, 2009: US07581219 (24 worldwide citation)

Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related to the sub-operating system mode using a dedicated virtual machine monitor (VMM) called the system man ...


5
Gilbert Neiger, Andrew V Anderson, Steven M Bennett, Jason Brandt, Erik Cota Robles, Stalinselvaraj Jeyasingh, Alain Kägi, Sanjoy K Mondal, Rajesh Parthasarathy, Dion Rodgers, Lawrence O Smith, Richard A Uhlig: Support for nested fault in a virtual machine environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 4, 2007: US07305592 (20 worldwide citation)

In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transitio ...


6
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Virtualization event processing in a layered virtualization architecture. Intel Corporation, Thomas R Lane, September 18, 2012: US08271978 (14 worldwide citation)

Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determin ...


7
Andy Glew, Michael A Kozuch, Erich S Boleyn, Lawrence O Smith III, Gilbert Neiger, Richard Uhlig: Method and apparatus for translating guest physical addresses in a virtual machine environment. Intel Corporation, Thomas R Lane, October 17, 2006: US07124273 (11 worldwide citation)

A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.


8
Gilbert Neiger, Steven M Bennett, Erik Cota Robles, Sebastian Schoenberg, Clifford D Hall, Dion Rodgers, Lawrence O Smith, Andrew V Anderson, Richard A Uhlig, Michael Kozuch, Andy Glew: System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 23, 2010: US07840962 (7 worldwide citation)

In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a ...


9
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Interrupt processing in a layered virtualization architecture. Thomas R Lane, March 1, 2011: US07900204 (5 worldwide citation)

Embodiments of apparatuses, methods, and systems for processing interrupts in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a recognition logic, window logic, and evaluation logic. The event logic is to recognize an interrupt request. The window logic ...


10
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Barry E Huntley, Lawrence O Smith: Injecting virtualization events in a layered virtualization architecture. Intel Corporation, Trop Pruner & Hu P C, April 3, 2012: US08151264 (5 worldwide citation)

Embodiments of apparatuses, methods, and systems for injecting virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to initiate a ...