1
Stephen P Gill, Lawrence F Wagner, Gregory G Frye, Klaus Peter A Bantowsky: Method and apparatus for speech recognition and reproduction. Votan, Owen Wickersham & Erickson, November 15, 1983: US04415767 (63 worldwide citation)

Speech signal analysis for data reduction, as stored for synthesis or recognition, is improved by features including: digital spectral analysis; reduction of channel data and bit allocation by selective summation of groups of contiguous data; using the mean average of the log amplitude to find the d ...


2
Wayne P Burleson, Lawrence F Wagner, Korbin S Van Dyke: Logarithmic conversion apparatus. VLSI Technology, Limbach Limbach & Sutton, December 2, 1986: US04626825 (29 worldwide citation)

A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer suc ...


3
Lawrence F Wagner, Wayne P Burleson, John P Guadagna: Comparator array logic. VLSI Technology, Limbach Limbach & Sutton, August 15, 1989: US04857882 (17 worldwide citation)

A comparator array logic (CAL) circuit has a plurality of interconnected comparators arranged in an array. Each of the comparators stores a digital value. The CAL circuit stores all of the digital values in a monotonically increasing or decreasing order. Each of the comparators receives the input da ...


4
Heemyong Park, Fariborz Assaderaghi, Jack A Mandelman, Ghavam G Shahidi, Lawrence F Wagner Jr: Integrated circuits with reduced substrate capacitance. International Business Machines Corporation, Eric W Petraske, May 13, 2003: US06562666 (17 worldwide citation)

Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device ...


5
Lawrence F Wagner, Korbin S Van Dyke, Wayne P Burleson, Robert D Hemming, John P Guadagna: Digital processor with a four part data register for storing data before and after data conversion and data calculations. VLSI Technology, Limbach Limbach & Sutton, April 28, 1992: US05109524 (13 worldwide citation)

A digital processor has a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Pr ...


6
Raminderpal Singh, Yue Tan, Jean Oliver Plouchart, Lawrence F Wagner Jr, Mohamed Talbi, John M Safran, Kun Wu: Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction. International Business Machines Corporation, H Daniel Schnurmann, November 21, 2006: US07139990 (12 worldwide citation)

A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as pr ...


7
Chang Ming Hsieh, Louis L G Hsu, Shaw Ning Mei, Ronald W Knepper, Lawrence F Wagner Jr: Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor. International Business Machines Corporation, Whitham Curtis Whitham & McGinn, December 6, 1994: US05371022 (10 worldwide citation)

A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width ...


8
Richard Kimmel, Lawrence F Wagner Jr: Method for obtaining DC convergence for SOI FET models in a circuit simulation program. International Business Machines Corporation, Tiffany L Townsend Esq, Ratner & Prestia, December 3, 2002: US06490546 (9 worldwide citation)

A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria a ...


9
George E Smith III, Fariborz Assaderaghi, Paul D Muench, Lawrence F Wagner Jr, Timothy L Walters: Method for use in simulation of an SOI device. International Business Machines Corporation, Lynn L Augspurger, October 31, 2000: US06141632 (8 worldwide citation)

A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose va ...


10
George E Smith III, Lawrence F Wagner Jr, Timothy L Walters, Fariborz Assaderaghi: Method for use in simulation of an SOI device. International Business Machines Corporation, Lynn L Augspurger, February 8, 2000: US06023577 (8 worldwide citation)

A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value ...