1
Larry B Weber, Craig C Hansen, Thomas J Riordan, Steven A Przybylski: Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders. Mips Computer Systems, Kenyon & Kenyon, September 25, 1990: US04959779 (81 worldwide citation)

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme ...


2
Larry B Weber, Earl A Killian, Mark I Himelstein: System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders. Silicon Graphics, Townsend and Townsend Khourie and Crew, March 14, 1995: US05398328 (42 worldwide citation)

A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte addr ...


3
Larry B Weber, Earl A Killian, Mark I Himelstein: System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders. Silicon Graphics, Sterne Kessler Goldstein & Fox P L L C, November 5, 1996: US05572713 (16 worldwide citation)

A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Li ...