1
Richard G Cliff, Srinivas T Reddy, Rina Raman, L Todd Cope, Joseph Huang, Bruce B Pedersen: Programmable logic array integrated circuit devices. Altera Corporation, Robert R Jackson, Fish & Neave, November 18, 1997: US05689195 (275 worldwide citation)

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated ...


2
Richard G Cliff, L Todd Cope, Cameron R McClintock, William Leong, James A Watson, Joseph Huang, Bahram Ahanin: Programmable logic array integrated circuits. Altera Corporation, Townsend and Townsend and Crew, August 27, 1996: US05550782 (248 worldwide citation)

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module wit ...


3
Richard G Cliff, L Todd Cope, Cameron McClintock, William Leong, James Allen Watson, Joseph Huang, Bahram Ahanin, Chiakang Sung, Wanli Chang: Programmable logic array integrated circuits. Altera Corporation, Robert R Jackson, Fish & Neave, October 27, 1998: US05828229 (136 worldwide citation)

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module wit ...


4
David E Jefferson, L Todd Cope, Srinivas Reddy, Richard G Cliff: System for distributing clocks using a delay lock loop in a programmable logic circuit. Altera Corporation, Townsend and Townsend and Crew, April 28, 1998: US05744991 (123 worldwide citation)

A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. ...


5
Richard G Cliff, L Todd Cope, Kerry Veenstra, Bruce B Pedersen: Look up table implementation of fast carry for adders and counters. Altera Corporation, Robert R Jackson, December 28, 1993: US05274581 (111 worldwide citation)

Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of ...


6
David E Jefferson, L Todd Cope, Srinivas Reddy, Richard G Cliff: System for distributing clocks using a delay lock loop in a programmable logic circuit. Altera Corporation, Townsend and Townsend and Crew, October 5, 1999: US05963069 (83 worldwide citation)

A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. ...


7
David E Jefferson, L Todd Cope, Srinivas Reddy, Richard G Cliff: Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution. Altera Corporation, Townsend and Townsend and Crew, October 10, 2000: US06130552 (72 worldwide citation)

A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase-locked loop (PLL) circuit in anot ...


8
Richard G Cliff, L Todd Cope, Cameron R McClintock, William Leong, James A Watson, Joseph Huang, Bahram Ahanin: Programmable logic array integrated circuits. Altera Corporation, Townsend and Townsend and Crew, October 17, 2000: US06134173 (67 worldwide citation)

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module wit ...


9
Richard G Cliff, L Todd Cope, Cameron R Mc Clintock, William Leong, James A Watson, Joseph Huang, Bahram Ahanin: Programmable logic array integrated circuits. Altera Corporation, Townsend and Townsend and Crew, September 22, 1998: US05812479 (61 worldwide citation)

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module wit ...


10
Richard G Cliff, L Todd Cope, Kerry Veenstra, Bruce B Pedersen: Programmable logic array circuits comprising look up table implementation of fast carry adders and counters. Altera Corporation, Robert R Jackson, Walter M Egbert III, Fish & Neave, July 20, 1999: US05926036 (60 worldwide citation)

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module wit ...