1
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components and wafer level methods of fabrication. Micron Technology, Stephen A Gratton, January 11, 2005: US06841883 (394 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


2
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Semiconductor component having plate, stacked dice and conductive vias. Micron Technology, Stephen A Gratton, March 3, 2009: US07498675 (97 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


3
Salman Akram, Kyle K Kirby: Through-substrate interconnect fabrication methods. Micron Technology, TraskBritt, September 19, 2006: US07109068 (87 worldwide citation)

A method for forming a conductive via or through-wafer interconnect (TWI) in a semiconductive substrate for use as a contact card, test connector, semiconductor package interposer, or die interconnect includes the acts of (a) forming an oxide or nitride layer on both sides of the substrate, (b) form ...


4
Sidney B Rigg, Charles M Watkins, Kyle K Kirby, Peter A Benson, Salman Akram: Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices. Micron Technology, Perkins Coie, August 15, 2006: US07091124 (77 worldwide citation)

Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad bein ...


5
Kyle K Kirby: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods. Micron Technology, Perkins Coie, September 18, 2007: US07271482 (66 worldwide citation)

Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individ ...


6
Kyle K Kirby, Salman Akram, David R Hembree, Sidney B Rigg, Warren M Farnworth, William M Hiatt: Microelectronic devices and methods for forming interconnects in microelectronic devices. Micron Technology, Perkins Coie, June 19, 2007: US07232754 (63 worldwide citation)

Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelec ...


7
Kyle K Kirby, Kunal R Parekh: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods. Micron Technology, Perkins Coie, October 4, 2011: US08030780 (61 worldwide citation)

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, ...


8
Kyle K Kirby: Probe card for use with microelectronic components, and methods for making same. Micron Technology, Perkins Coie, August 2, 2005: US06924655 (57 worldwide citation)

The present disclosure provides probe cards which may be used for testing microelectronic components, including methods of making and using such probe cards. One exemplary implementation provides a probe card that employs a substrate with a plurality of openings. A first probe, which may be used to ...


9
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Wafer level methods for fabricating multi-dice chip scale semiconductor components. Micron Technology, Stephen A Gratton, June 13, 2006: US07060526 (57 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


10
Kyle K Kirby, William M Hiatt, Richard L Stocks: Microfeature workpieces and methods for forming interconnects in microfeature workpieces. Micron Technology, Perkins Coie, August 28, 2007: US07262134 (48 worldwide citation)

Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to ...