1
Leslie D Kohn, Kunle A Olukotun, Michael K Wong: DRAM power management. Sun Microsystems, Martine Penilla & Gencarella, August 30, 2005: US06938119 (137 worldwide citation)

A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. ...


2
Leslie D Kohn, Kunle A Olukotun, Michael K Wong: Multi-core multi-thread processor. Sun Microsystems, Martine Penilla & Gencarella, April 24, 2007: US07209996 (43 worldwide citation)

In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plu ...


3
Kunle A Olukotun: Multi-core multi-thread processor. Oracle America, Martine Penilla & Gencarella, January 18, 2011: US07873785 (9 worldwide citation)

A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plu ...


4
Kunle A Olukotun: Request arbitration in multi-core processor. Sun Microsystems, Martine Penilla & Gencarella, November 7, 2006: US07133950 (7 worldwide citation)

A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabli ...


5
Kunle A Olukotun: Multi-core multi-thread processor crossbar architecture. Oracle America, Martine Penilla Group, June 11, 2013: US08463996

A processor chip is provided. The processor chip includes a plurality of processing cores where each of the processing cores being multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabl ...


6
Kunle A Olukotun: Cache crossbar arbitration. Sun Microsystems, Martine Penilla & Gencarella, March 17, 2005: US20050060457-A1

A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabli ...


7
Kunle A Olukotun: Multi-core multi-thread processor. Sun Microsystems, Martine & Penilla & Gencarella, February 24, 2005: US20050044319-A1

A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plu ...


8
Kunle A Olukotun: Cache bank interface unit. Sun Microsystems, Martine & Penilla & Gencarella, February 24, 2005: US20050044320-A1

A server including an application processor chip. The application processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. A plurality of cache bank memories is included. Each of the cache bank memories include a tag array region configured to s ...


9
Leslie D Kohn, Kunle A Olukotun, Michael K Wong: Multi-core multi-thread processor. Martine Penilla & Gencarella, July 12, 2007: US20070162911-A1

In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plu ...


10
Leslie D Kohn, Kunle A Olukotun, Michael K Wong: Dram power management. Sun Microsystems, Martine & Penilla, May 15, 2003: US20030093614-A1

A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. ...