1
Kunihiko Nakada, Yasushi Akao: Integrated CPU and DMA with shared executing unit. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, April 2, 1991: US05005121 (26 worldwide citation)

A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory ...


2
Yoshiyuki Miwa, Tsuyoshi Jouno, Haruo Keida, Kunihiko Nakada, Hajime Yasuda: Semiconductor integrated circuit device with test mode for testing CPU using external signal. Hitachi, Hitachi Microcomputer Engineering, Fay Sharpe Beall Fagan Minnich & McKee, July 13, 1993: US05228139 (21 worldwide citation)

An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provid ...


3
Kunihiko Nakada: Data processor and microcomputer. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, October 5, 1999: US05961578 (16 worldwide citation)

In a microcomputer incorporating a microprocessor, the coprocessor having product-sum operation arithmetic units executes residue multiplications given by "A=A.multidot.B.multidot.R.sup.-1 mod N+kN", "A=A.sup.2 .multidot.R.sup.-1 mod N+kN" and "A=A.multidot.R.sup.-1 mod N 30 kN" and is provided with ...


4
Masahiro Kaminaga, Takashi Endo, Masaru Ohki, Takashi Tsukamoto, Hiroshi Watase, Chiaki Terauchi, Kunihiko Nakada, Nobutaka Nagasaki, Satoshi Taira, Yuuichirou Nariyoshi, Yasuko Fukuzawa: Information processing device, card device and information processing system. Hitachi, Hitachi ULSI Systems, Mattingly Stanger Malur & Brundidge P C, August 1, 2006: US07086087 (14 worldwide citation)

It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first infor ...


5
Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi: IC card and microprocessor. Renesas Technology, Hitachi ULSI Systems, Miles & Stockbridge P C, June 14, 2005: US06907526 (12 worldwide citation)

Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminal ...


6
Yoshiyuki Miwa, Tsuyoshi Jouno, Haruo Keida, Kunihiko Nakada, Hajime Yasuda: Semiconductor integrated circuit device with test mode for testing CPU using external Signal. Hitachi, Hitachi Microcomputer Engineering, Fay Sharpe Beall Fagan Minnich & McKee, December 3, 1996: US05581698 (10 worldwide citation)

An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provid ...


7
Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto: Information processing device. Hitachi, Hitachi ULSI Systems, Stanley P Fisher Esq, Juan Carlos A Marquez Esq, Reed Smith, February 17, 2004: US06691921 (10 worldwide citation)

An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least ...


8
Hisao Sasaki, Takeshi Miyazaki, Shiro Baba, Kunihiko Nakada, Yasushi Akao: Integrated data processor having mode control register for controlling operation mode of serial communication unit. Hitachi, Antonelli Terry Stout & Kraus, July 6, 1993: US05226173 (9 worldwide citation)

A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop ...


9
Masahiro Izutsu, Kunihiko Nakada, Michimasa Suzawa: Download method for file by bit torrent protocol. Grid Solutions, Oliff & Berridge, May 27, 2008: US07379967 (9 worldwide citation)

The present invention relates to the improvement of the Bit Torrent protocol, which is one of the P2P protocols. A seeder flag is added to the active peer table. First a super seeder having the original is activated, and the super seeder is stopped when the total value of the seeder flags (number of ...


10
Hisao Sasaki, Takeshi Miyazaki, Shiro Baba, Kunihiko Nakada, Yasushi Akao: Integrated data processor having mode control register for controlling operation mode of serial communication unit. Hitachi, Antonelli Terry Stout & Kraus, November 1, 1994: US05361374 (8 worldwide citation)

A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchron ...