1
Dakshina Murthy Srikanteswara, An Judy Xilin, Krivokapic Zoran, Wang Haihong, Yu bin: Strained channel finfet. Advanced Micro Devices, Dakshina Murthy Srikanteswara, An Judy Xilin, Krivokapic Zoran, Wang Haihong, Yu bin, sCOLLOPY Daniel R, August 12, 2004: WO/2004/068585 (4 worldwide citation)

A semiconductor structure includes a fin (205) and a layer (305) formed on the fin. The fin (205) includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer (305) is formed on the surfaces and includes a second crystalline material. The first crystal ...


2
Krivokapic Zoran, Spence Christopher A: Attenuated phase shift mask and process for fabricating such a mask. Advanced Micro Devices, December 13, 1995: EP0686876-A2 (3 worldwide citation)

An attenuated phase shift mask comprises a first layer having a thickness to provide a transmission in the range of about 3 to 10% formed on a transparent substrate and a second layer comprising a transparent material having a thickness to provide a desired phase shift, formed on said first layer. F ...


3
Krivokapic Zoran, An Judy Xilin, Dakshina Murthy Srikanteswara, Wang Haihong, Yu bin: Narrow fin finfet. Advanced Micro Devices, Krivokapic Zoran, An Judy Xilin, Dakshina Murthy Srikanteswara, Wang Haihong, Yu bin, sCOLLOPY Daniel R, August 12, 2004: WO/2004/068589 (3 worldwide citation)

A narrow channel FinFET is described herein with a channel width of less than 6 nm. The FinFET may include a fin (140) in which the channel area is trimmed using a NH4OH etch or a reactive ion etch (RIE).


4
Lin Ming Ren, Krivokapic Zoran, Maszara Witek: Method of forming finned semiconductor devices with trench isolation. Advanced Micro Devices, Lin Ming Ren, Krivokapic Zoran, Maszara Witek, Drake Paul S, January 28, 2010: WO/2010/011287 (2 worldwide citation)

A method of manufacturing a semiconductor device structure (300), such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material (302), a first conductive fin structure (306) formed from the bulk semiconductor material (302), and a ...


5
Xiang Qi, Subba Niraj, Maszara Witold P, Krivokapic Zoran, Lin Ming Ren: Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor. Advanced Micro Devices, Xiang Qi, Subba Niraj, Maszara Witold P, Krivokapic Zoran, Lin Ming Ren, DRAKE Paul S, May 18, 2006: WO/2006/052379 (1 worldwide citation)

A semiconductor substrate (102) is provided having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104). A deep trench isolation (108) is formed, introducing strain to the semiconductor layer (106). A gate dielectric (202) and a gate (204) are formed on the semiconducto ...


6
Tabery Cyrus E, Ahmed Shibly S, Buynoski Matthew S, Dakshina Murphy Srikanteswara, Krivokapic Zoran, Wang Haihong, Yang Chih Yuh, Yu bin: Self aligned damascene gate. Advanced Micro Devices, Tabery Cyrus E, Ahmed Shibly S, Buynoski Matthew S, Dakshina Murphy Srikanteswara, Krivokapic Zoran, Wang Haihong, Yang Chih Yuh, Yu bin, sDRAKE PAUL S, May 26, 2005: WO/2005/048339 (1 worldwide citation)

A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320 ...


7
Lin Ming Ren, An Judy Xilin, Krivokapic Zoran, Tabery Cyrus E, Wang Haihong, Yu bin: Double and triple gate mosfet devices and methods for making same. Advanced Micro Devices, sCOLLOPY Daniel R, May 6, 2004: WO/2004/038808 (1 worldwide citation)

A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin (220), a first gate (240) and a second gate (420). The first gate (240) is formed on top of the fin (220). The second gate (420) surrounds the fin (220) and the first gate (240). In another implementation, a trip ...


8
Krivokapic Zoran, Collopy Daniel R: Strained semiconductor device and method of manufacture. Advanced Micro Devices, March 29, 2006: GB2418533-A

A strained semiconductor device suitable for use in an integrated circuit and a method for manufacturing the strained semiconductor device. A mesa isolation structure is formed from a semiconductor on-insulator substrate. A gate structure is formed on the mesa isolation structure. The gate structure ...


9
Tabery Cyrus E, Ahmed Shibly S, Buynoski Matthew S, Dakshina Murphy Srikanteswara, Krivokapic Zoran, Wang Haihong, Yu bin, Yang Chih Yuh: Self aligned damascene gate. Advanced Micro Devices, September 27, 2006: GB2424517-A

A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320 ...


10
Yu bin, Ahmed Shibly S, An Judy Xilin, Dakshina Murthy Srikanteswara, Krivokapic Zoran, Wang Haihong: Semiconductor device having a u-shaped gate structure. Advanced Micro Devices, June 29, 2005: GB2409575-A

A double-gate semiconductor device (100) includes a substrate (110), an insulating layer (120), a fin (210) and agate (510). The insulating layer (120) is formed on the substrate (110) and the gate (510) is formed on the insulating layer (120). The fin (210) has a number of side surfaces, a top surf ...



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