41
Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazushi Kurata, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Snell & Wilmer, September 4, 2008: US20080215858-A1

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


42
Hiroyuki Morishita, Kosuke Yoshioka, Hideshi Nishida, Makoto Hirai, Ryuji Matsuura, Toshiaki Tsuji, Kozo Kimura, Tokuzo Kiyohara: Pixel calculating device. Joseph W Price, Price & Gess, January 9, 2003: US20030007565-A1

A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filterin ...


43
Hiroyuki Oka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara, Makoto Hirai, Kozo Kimura, Ryuji Matsuura, Hiroyuki Morishita, Toshiaki Tsuji: Pixel calculating device. Joseph W Price, Price & Gess, August 8, 2002: US20020106136-A1

A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supp ...


44
Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura: Circuit group control system. Snell & Wilmer, May 12, 2005: US20050102440-A1

A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the com ...


45
Kozo Kimura, Tokuzo Kiyohara, Hiroshi Mizuno, Junji Michiyama, Tomohiko Kitamura, Ryoji Yamaguchi, Manabu Kuroda, Nobuhiko Yamada, Hideyuki Ohgose, Akifumi Yamana: Integated Circuit For Video/Audio Processing. Matsushita Electric Industrial, Greenblum & Bernstein, December 13, 2007: US20070286275-A1

The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream ...


46
Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazushi Kurata, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Snell & Wilmer, August 28, 2008: US20080209162-A1

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


47
Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazushi Kurata, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Snell & Wilmer, August 28, 2008: US20080209192-A1

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


48
Hideshi Nishida, Takeshi Furuta, Tetsuya Tanaka, Kozo Kimura, Tokuzo Kiyohara: Information processing apparatus and exception control circuit. Wenderoth Lind & Ponack, February 19, 2009: US20090049219-A1

To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular proce ...


49
Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara: Microprocessor. Snell & Wilmer, July 17, 2003: US20030135779-A1

A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform dat ...


50
Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida: Circuit group control system. Snell & Wilmer, June 12, 2003: US20030110329-A1

A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the com ...