1
Kozo Kimura, Tokuzo Kiyohara, Kousuke Yoshioka: Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream. Matsushita Electric Industrial, Price Gess & Ubell, August 15, 2000: US06105127 (114 worldwide citation)

A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for r ...


2
Kozo Kimura, Hiroaki Hirata: Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream. Matsushita Electric Industrial, Price Gess & Ubell, August 13, 1996: US05546593 (83 worldwide citation)

The present invention discloses a multistream instruction processor issuing instructions from N instruction streams in parallel, and processing instruction streams interchangeably when the number of the instruction streams is N or larger than N. Such processor comprises aninstructionpreparationunit ...


3
Kozo Kimura, Kosuki Yoshioka, Tokuzo Kiyohara: Speculative execution processor. Matsushita Electric Co, Price Gess & Ubell, April 23, 1996: US05511172 (43 worldwide citation)

The present invention discloses a speculative execution processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored in its memory. The processor comprises an instruction type distinguishing device for distinguishing a ty ...


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Hiroaki Hirata, Kozo Kimura: Cache block replacement scheme based on directory control bit set/reset and hit/miss basis in a multiheading multiprocessor environment. Matsushita Electric Industrial, Price Gess & Ubell, July 9, 1996: US05535361 (30 worldwide citation)

A cache controller for a multithreading multiprocessor system which starts an execution of another thread by suspending an ongoing execution of a thread when a cache miss happens. The cache controller comprises a cache directory unit for storing cache managing data including a footprint bit to indic ...


6
Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura: Media processing apparatus which operates at high efficiency. Matsushita Electric Industrial, Price and Gess, October 30, 2001: US06310921 (30 worldwide citation)

A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the inp ...


7
Kozo Kimura, Tokuzo Kiyohara, Toshimichi Matsuzaki: Processing system for branch instruction. Matsushita Electric Industrial, Lowe Price LeBlanc & Becker, March 23, 1993: US05197136 (25 worldwide citation)

A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. Th ...


8
Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura: Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system. Matsushita Electric Industrial, Price Gess & Ubell, June 13, 2000: US06075899 (25 worldwide citation)

An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominanc ...


9
Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Matsushita Electric Industrial, June 10, 2008: US07386707 (16 worldwide citation)

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


10
Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Panasonic Corporation, Panasonic Patent Center, Dhiren Odedra, Kerry Culpepper, April 19, 2011: US07930520 (15 worldwide citation)

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...