1
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags. Nexgen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226126 (369 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


2
John S Yates Jr, David L Reese, Korbin S Van Dyke: Recording in a program execution profile references to a memory-mapped active device. ATI International, David E Boundy Esq, Schulte Roth & Zabel, May 28, 2002: US06397379 (192 worldwide citation)

A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instr ...


3
Korbin S Van Dyke: Method and apparatus for restricting memory access. ATI International S R L, Vedder Price Kaufman & Kammholz, November 20, 2001: US06321314 (185 worldwide citation)

A method and apparatus for restricting memory access includes processing that begins by monitoring memory access requests. When one of the memory access requests is requesting access to restricted memory, determining the mode of operation of the processor. Note that the mode of operation of the proc ...


4
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Method and apparatus for debugging an integrated circuit. Advanced Micro Devices, B Noël Kivlin, Conley Rose & Tayon PC, December 24, 2002: US06499123 (154 worldwide citation)

An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second ...


5
Korbin S Van Dyke, Paul Campbell, Don Alan Van Dyke: Computer for execution of RISC and CISC instruction sets. ATI International, David E Boundy, Willkie Farr & Gallagher, May 16, 2006: US07047394 (147 worldwide citation)

A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instruction ...


6
John S Yates, David L Reese, Korbin S Van Dyke: Detecting modification to computer memory by a DMA device. ATI International, Joel E Lutzker, David E Boundy, Schulte Roth & Zabel, April 15, 2003: US06549959 (144 worldwide citation)

A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided ...


7
David L Puziol, Korbin S Van Dyke, Larry Widigen, Len Shar, Walstein B Smith III: Configurable branch prediction for a processor performing speculative execution. NexGen, W Bennett Smith III, September 26, 1995: US05454117 (127 worldwide citation)

In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hard ...


8
John S Yates Jr, David L Reese, Korbin S Van Dyke: Recording classification of instructions executed by a computer. ATI International, David E Boundy, Willkie Farr & Gallagher, October 11, 2005: US06954923 (114 worldwide citation)

An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instruction ...


9
Korbin S Van Dyke, Paul H Hohensee, David L Reese, John S Yates Jr, T R Ramesh, Shalesh Thusoo, Gurjeet Singh Saund, Stephen C Purcell, Niteen Aravind Patkar: Profiling execution of computer programs. ATI International, David E Boundy, Willkie Farr & Gallagher, March 14, 2006: US07013456 (113 worldwide citation)

A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with th ...


10
Richard Hessel, Chetana N Keltcher, Nathan Daniel Tuck, Korbin S Van Dyke: Vector processor system. West & Associates A PC, Stuart J West, Shaun Sluman, January 15, 2013: US08356144 (104 worldwide citation)

A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces co ...