1
Yasunobu Nakase, Koji Nii: Semiconductor memory device capable of generating internal data read timing precisely. Renesas Technology, McDermott Will & Emery, July 6, 2004: US06760269 (181 worldwide citation)

Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating ...


2
Koji Nii, Atsushi Miyanishi: Semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Leydig Voit & Mayer, February 12, 2002: US06347062 (115 worldwide citation)

In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well ...


3
Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Semiconductor memory device. Renesas Technology, McDermott Will & Emery, March 10, 2009: US07502275 (110 worldwide citation)

Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a float ...


4
Yasumasa Tsukamoto, Koji Nii: Semiconductor memory device with back gate potential control circuit for transistor in memory cell. Renesas Technology, McDermott Will & Emery, July 18, 2006: US07079413 (70 worldwide citation)

A substrate potential setting circuits are provided which control substrate potentials in units of columns of a memory cell array at least in data writing. Upon data writing, the potential of the substrate region of memory cell transistors on a selected column is changed to reduce the data holding c ...


5
Hiroshi Matsumura, Koji Nii: Grip tape. Asahi Kagaku Kogyo, Lowe Price Leblanc & Becker, October 8, 1991: US05055340 (63 worldwide citation)

A grip tape for wrapping the gripping handle of a tennis racket, a badminton racket, a golf club, or the like which includes a porous flexible sheet with numerous thin holes provided by coating a polyurethane on a nonwoven fabric so as to provide the user with various effects such as a smooth touch ...


6
Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii: Semiconductor integrated circuit device. Renesas Technology, Reed Smith, Stanley P Fisher Esq, Juan Carlos A Marquez Esq, September 26, 2006: US07113421 (62 worldwide citation)

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with mu ...


7
Koji Nii: Semiconductor memory device capable of controlling potential level of power supply line and/or ground line. Renesas Technology, McDermott Will & Emery, June 7, 2005: US06903962 (51 worldwide citation)

Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are s ...


8
Koji Nii: Semiconductor memory device. Renesas Technology, McDermott Will & Emery, May 25, 2004: US06741492 (36 worldwide citation)

In a semiconductor memory device of the present invention, four access transistors of two memory cells arranged adjacent to each other in the same row are formed within a common p-type well, and each gate of access transistors of memory cell and each gate of access transistors and of memory cell are ...


9
Koji Nii, Atsushi Miyanishi: Semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Leydig Voit & Mayer, March 18, 2003: US06535453 (35 worldwide citation)

In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well ...


10
Tomoaki Yoshizawa, Koji Nii, Susumu Imaoka: Semiconductor memory device internally generating internal data read timing. Renesas Technology, Renesas Device Design, McDermott Will & Emery, October 12, 2004: US06804153 (27 worldwide citation)

A dummy circuit including a plurality of dummy cells is provided in correspondence to a predetermined number of word lines. When either one of corresponding word lines are selected, a dummy bit line equal in load to a normal bit line is driven using the plurality of dummy cells included in this dumm ...



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